Configuration pins 10M02SCE144I7G

[JRe2s]

Hello Team,

could you review the attached schematics? In particular the config pins of the FPGA?

Best regards,

Jochen

[FvM]

Why are you connecting JTAGEN to JTAG connector pin 8?

[JRe2s]

Maybe this is wrong wired. Should the JTAGEN be pulled high or low if the pin is not used as an IO?

[FvM]

JTAGEN should be pulled high by 10k to enable JTAG pins in user mode. Or configure JTAGEN in dual purpose pin setup as IO to enable JTAG pins unconditionally.

[JRe2s]

OK, thanks. The other config pins are wired correct?

[FvM]

Yes, think so.

[Fakhrul]

Hi JRe2s,

Alternatively, you can check by referring to the Intel® MAX® 10 Schematic Review Worksheet on Section II, Configuration. (https://www.intel.com/content/www/us/en/content-details/650218/intel-max-10-schematic-review-worksheet.html?DocID=650218)

Regards,

Fakhrul

[Fakhrul]

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