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Connect External Arm DSTREAM Debugger and Arm Development Studio with Intel Stratix 10 SX DK

SSB
Novice
389 Views

Hi all,

I have my Intel Stratix 10 SX Development Kit up and running with FPGA design programmed into SDM QSPI flash via USB-Blaster II cable. U-Boot does run on the Cortex-A53 core when board boots up and I am able to deploy and run my hello world application on top of U-Boot on the A53 core.

I am now interested to debug my application using external Arm DSTREAM JTAG debugger by connecting to the Cortex-A53 cores and debugging it via Arm Development Studio v2022.0 . At the moment Arm DS is unable to connect to the A53 cores and gives an error that a "Stratix 10 device has not been recognized". Can someone please guide me what switch settings should I use so the A53 cores are added to the scan chain ? Please find below my current switch settings:

 

SW1 [1-8]: off, off, on, on, on, on, on, on
SW2 [1-4]: on, off, off, off
SW3 [1-4]: off, off, off, off
SW4 [1-4]: on, off, off, on
SW8 [1-2]: off, off

 

Best Regards.

0 Kudos
8 Replies
JingyangTeh
Employee
361 Views

Hi


You could refer to the document on setting up the ARM DS.

https://www.intel.com/content/www/us/en/docs/programmable/683211/current/using-ds-5-ae-to-create-and...


Regards

Jingyang, Teh


SSB
Novice
334 Views

Hi,

Thanks for the response. The document you mentioned above does not point on how configure the FPGA image to include the HPS into the JTAG scan chain and carry out debug via external JTAG.

 

Any help around that area is appreciated. At the moment, on launching a debug connection, ARM DS complains that the connected device is not recognized as a Stratix10 platform.

 

Thanks.

JingyangTeh
Employee
296 Views

Hi


Did you follow the steps in creating the debug configuration to the board?

https://www.intel.com/content/www/us/en/docs/programmable/683211/current/debug-the-project.html

You will need to select the Stratix10 platform.


Regards

Jingyang, Teh


JingyangTeh
Employee
274 Views

Hi


Any update on this case?


Regards

Jingyang, Teh


JingyangTeh
Employee
249 Views

Hi


Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


SSB
Novice
202 Views

Hi Jingyang, Teh

 

Thanks a lot for the response. Essentially it seem like that the HPS JTAG is not visible to the debugger at all. This is what the SPL and U-Boot prompt looks like :

U-Boot SPL 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)
Reset state: Cold
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1105 ms
QSPI: Reference clock at 400000000 Hz
WDT:   Not found!
Trying to boot from MMC1


U-Boot 2019.10-ga2f8989-dirty (May 13 2020 - 22:36:10 +0800)socfpga_stratix10, 6

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM:  4 GiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 9a:94:bf:47:78:41
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
SOCFPGA_STRATIX10 #

 

Do I need to deploy a different reference design to make HPS JTAG visible in the scan chain ? Any steps for configuring such a design ?

SSB
Novice
186 Views

Note that I am using HPS IO-48 Daughter card and using the Mictor 38 Pin connector for HPS JTAG access.

JingyangTeh
Employee
95 Views

Hi SSB


I see that there is a separate case that is similar that you have created.

https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Use-Mictor-38-HPS-JTAG-on-HPS-IO-48-OOBE...


Could we close this case and follow it up on the other case?


Regards

Jingyang, Teh


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