Controlling proto1_RESET on NiosII Dev Board

[Altera_Forum]

Hi, 

I am trying to communication with a HDD over the Proto1 connector on a NiosII Dev Board Cyclone II Edition. The reset is pin 1; however, pin 1 is hard-wired to pin 56 of U3 which provides the reset to the Proto1 connector. But I need to control the Reset. Has anyone ran into problems with not being able to control the reset pin on the Proto1 connector? Why did Altera hard-wire it? Thanks for any help that you can provide. -Ben

[Altera_Forum]

Don't see why you need to control the reset to IDE interface. Most PC and embedded IDE interfaces have the reset hardwired to system reset, I never experienced this to be a problem. IDE has a software reset, too.

[Altera_Forum]

Hi FvM, can you go into a little more detail (I am still learning how to communicate with the HDD). The ATA manual states that "RESET- (Drive reset) This signal from the host system shall be asserted for at least 25 usec after voltage levels have stabilized during power on and negated thereafter". I was under the assumption that I had to control the RESET- pin with this timing.  

 I am a little confused at what you mean by the Software Reset. I just noticed that there is a DEVICE RESET command that I can send to the HDD. Is this what you meant. I will try this out next. Thanks for the fast reply, -Ben

[Altera_Forum]

ATA specification defines 9.2 software reset protocol, that is functional equivalent to hardware reset 9.1 power-on and hardware reset protocol. Apart from that, you can expect, that the hardwired system reset will also generate a suitable hardware reset.