Cyclone 10 LP nConfig problem

[omriL]

Hi,

I have a project where I have connected the nConfig pin of the Cyclone 10 LP thru FET (drain pin) with PU.

the gate of the FET is connected to GPIO of bank 8 (3.3V), and the source connected to GND.

On power up the state of the GPIO is as desined in the FAB and it become high - so the FET is saturated and the nConfig pin is driven low.

this issue generate a loop where the FPGA can not finish the init proccess and I have to remove the serial resistor from the gate of the FET to let the FPGA finish the init proccess.

this connection was on my previous design with Cyclone 3 and it worked well.

Is there any reason why it is happaning? 

Can I chnage the state of the GPIO before the init proccess finish? (there is a way to set GPIOs as weak Pull-Up but no weak Pull-Down)

thanks for the help 

[FvM]

Hi,
the usual solution is to connect a pull-down overriding weak pull-up, value depending on FET Vth e.g. 470R to 1k.

[omriL]

Hi FvM,

Thanks for the  help,

will try and share the resualts,

BR,

Omri

[Fakhrul]

Hi OmriL,

FvM is correct. You can also set the I/O to weak pull-up during configuration.

Best regards,

Fakhrul

[Fakhrul]

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