Is there any specifications for the interfaces between Cyclone 10LP and MAX10 devices on the Intel Cyclone 10LP Evaluation Kit?
The "golden system reference design" projects defines a couple of interfaces that is not described in the manual, nor found anywhere in examples or template projects - namely the "Side Bus", clearly carrying signals related to some USB fifo functionality, and 4-line all-inout "Cyclone 10 to MAX 10 IO" bus.
Is it possible to get a description of the protocols on those interfaces? Is it implemented in the MAX10 System Controller at all?
Welcome to INTEL forum. There is no special specifications for the interfaces connection between Cyclone 10LP and MAX10 devices on the Intel Cyclone 10LP Evaluation Kit. it’s just regular IO connection between 2 FPGA
Those lines can't be a regular IO, they are not exposed on the external connectors, and there are no ways to put your own design into the MAX10 device to make use of those IOs.
As a matter of fact, exactly the same interface could be found on another Intel kit - DK-DEV-10M50-A, connecting the main MAX10 device and the MAX II CPLD. And it's also not exposed to board connectors and not described.
Both these kits have a common distinction from all the other boards with onboard USB BLASTER II, they do have two USB interfaces, not just one. And it's my guess that the presence of one extra USB interface in the USB device description (as seen with USBView) has to be connected to the fact that there's a FIFO-like interface defined between the main FPGA and the chip implementing USB interfaces.
It's hard to believe two kits produced at the different time would have the same idea designed into the hw just to be left abandoned.
I am not sure on what is the specific enquiry and your plans to do here but the board design management chip (Max 10) here is proprietary design which is beyond dev kit support coverage. Intel mainly sells the dev kit to promote FPGA device and FPGA feature usage but the board design. We support on FPGA related enquiry, but board design is different topic.
It's not about system management chip (Max 10) design or internals.
The Cyclone 10LP kit does not provide any USB connections to the user designs in the Cyclone 10LP fpga.
Seeing the set of usb-related lines on a schematics, and seeing same lines defined as regular IO in the gold reference design project I realized I could use that interface to communicate with my designs, implementing own IPs to serve the USB transfers on those lines.
Since the lines are not connected to any dedicated hardware functionality on the Cyclone 10LP fgpa I came to a conclusion that interface requires an IP to be implemented on the fpga side, so from the very beginning this interface was intended to be used for communications with the user designs in Cyclone 10LP fpga over the USB, regardless of the implementation details of the system management facilities.
It's unfortunate the protocol between USB endpoints and usb-related lines going into Cyclone 10LP is not described. I'm not asking for designs or IPs, just the definition of the protocol which must exist, because same interface is found on two different Intel fpga kits. And I thought since this is a board for "FPGA/SoC/CPLD boards and kits" discussions, someone could shed some light on that particular detail of the Cyclone 10LP evaluation kit.
Thanks for the explanation. Based on my understanding, Intel FPGA don’t provide USB IP solution and Intel leverages design service from 3rd party to manage the USB design solution implementation. Therefore, there is no plan to share more info about the USB connection detail. Please accept my apologies for not being able to assist you fully on USB design solution.
We have not heard from you and I hope that my last note clears up this matter. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.