Cyclone IV GX starter kit SSRAM access

[Altera_Forum]

Hi, if anyone made the link work, could you share a link or some tips? I checked the schematic. It seems the control signals to the ISSI SSRAM need to go through the MAX II chip(EPM2210) since the Cyclone IV GX doesn't control the ADSP#, ADSC#, and ADV# signals. Does it mean I need to have the SRAM controller inside the EPM2210 and send data to/from the Cyclone IV GX chip? 

Thanks, Mark

[Altera_Forum]

The reference design has an example of SSRAM/MaxII interface under Qsys. I am going to try it. But, I thought there should be a way for us to send signals directly to the ISSI SSRAM/MaxII?

[Altera_Forum]

I watched some SRAM signals on SignalTap. It doesn't seem that the controller puts the chip in burst mode? The chip spec says it can work at 250MHz clock(500Mbytes/s). I wondered if anyone tried at least at 200MHz. BTW, I used the bts_general sample code.

[Altera_Forum]

I set the first data to 0x12345678 and saw it on SignalTap on the FSML bus for both read and write, cool. But it takes about 40 clocks at 50MHz to get that 4 bytes of data out. Maybe I didn't set some parameters properly in Qsys for the CFI related components. I would expect a date rate comparable to a DDR device(maybe a bit slower since it has only a 16bit data bus).

[Altera_Forum]

It looks like the JTAG to Avalon Master Bridge used in bts_general sample code doesn't support burst transfers. Since the bridge has a 32bits bus and the SRAM has 16bits so there is a burst of 2 transfers seen on the SRAM data bus. I would expect the 2 data transfers on the SRAM bus take 2 clocks but it takes a lot more as seen on SignalTap(of course, if you consider the command on the SRAM bus it would take more than 2 clocks but 2 clocks are enough for the data only). Maybe there is a way to optimize the timing of the transfer by choosing the parameters.