Cyclone V - CLK[0:11][P:N] Connection

[royroif]

Hi,

In our schematics we have some of the CLK[0:11]P pins used as single-ended input clocks and related CLK[0:11]N pins connected with 5K pull-down resistor to GND.

I saw in the Cyclone V documentation:

1. In Cyclone V documentation Intel recommend to tie the CLK[0:11]N pins to GND or leave them unconnected and configure them as internally bias in Quartus.

2. In Cyclone V EVK schematics Intel tied the CLK[0:11]N pins to GND.

Please your support understanding what is the impact of connecting the CLK[0:11]N pins with 5K pull-down resistor to GND instead of tied to GND?

Thanks,

Roy Roif

[FvM · Accepted solution]

Hi,

"Please your support understanding what is the impact of connecting the CLK[0:11]N pins with 5K pull-down resistor to GND instead of tied to GND?"

I don't see 5k pull-down for unused clock input suggested in an Intel document, and I don't see a specific advantage or "impact".

Cyclone V is providing weak pull-up and other options to bias unconnected input pins, different from other FPGA families, the option is also available for clock pins. We see grounded unused clock pins with other FPGA families that don't have this bias option for clock pins.

Pull-down resistors are partly suggested for unused refclock inputs of gigabit transceivers. These pins use different I/O standards and have therefore different requirements. It makes no sense to copy the suggestion for standard clock inputs.

[royroif]

Hi FvM,

Thank you for your reply.

Just to clarify:

In case of connecting a single-ended input clock, negative pin considered as unused input pin? isnt it the return path of this specific logic?

Thanks,

Roy Roif

[FvM]

Hi Roy,
the return path for single ended I/O is GND.

[royroif]

Hi FvM,

So in case of connecting a single-ended input clock, negative pin considered as unused input pin and should be tied to GND or internally biased?

Thanks,

Roy Roif

[AqidAyman_Intel]

Hello Roy,

It can be both, depending on your design.

"When you use the single-ended I/O standard, only the CLK[0:11]p pins serve as the dedicated input."

"When you do not use these pins, Altera recommends tying them to GND or leaving them unconnected. If these pins are unconnected, use the Quartus Prime software programmable options to internally bias these pins."

You can refer to the Pin Connection Guidelines for the pin named "CCLK[0:11][p:n]" on page 2 from Cyclone® V GX, GT, E, SX, ST and SE Device Family Pin Connection Guidelines documentation. Refer to below link:

https://www.intel.com/content/www/us/en/content-details/654351/cyclone-v-gx-gt-e-sx-st-and-se-device-family-pin-connection-guidelines.html

Regards,

Aqid

[AqidAyman_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.