FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5279 Discussions

Cyclone V GX transceiver Native PHY IP

S_Healthineers
Beginner
475 Views

Does anyone know where to find a reference design for Cyclone V transceiver Native PHY IP with reset and reconfiguration controller

0 Kudos
2 Replies
CheePin_C_Intel
Employee
225 Views

Hi,

 

As I understand it, you have some inquiries related to example design for CV dynamic reconfiguration. For your information, I have sent you a simulation example which was previously available in wiki for your reference. Please let me know if there is any concern. Thank you.

S_Healthineers
Beginner
225 Views

​Thanks 😃

Reply