I am occupied with the baremetal ethernet implementation on a Cyclone V SoC DE10 nano board.
In the 'Cyclone V Hard Processor System Technical Reference Manual' (cv_5v4 2019.06.14) (chapter ‘EMAC HPS Interface Initialization’ on page 18-66) is the following instruction:
“3. Bring the Ethernet PHY out of reset to verify that there are RX PHY clocks.”
How is it possible to verify if there are RX PHY clocks by means of SW? Since I am using the EMAC1 the RX PHY clock is connected to Pin ‘RGMII1_RX_CLK’ of the HPS portion. I also tried to read the ALT_EMAC1_GMAC_SGMII_RGMII_SMII_CTL_STAT_ADDR register to check the link to the PHY. Is this the correct way? Unfortunately I read just 0x0000 which seem to be the reset values.
May I know which Quartus version you are working on?.
Based on the document, firstly the Ethernet Controller must be in a reset state during static configuration, then the clock must be active and valid before the Ethernet Controller is brought out of reset.
I am using Quartus Prime 17.1.
But how can I verify if the PHY clocks are there? The manual just says "Bring the Ethernet PHY out of reset to verify that there are RX PHY clocks". The PHY was released from reset and all the configured clocks were setup.
To verify the RX PHY clock, after bringing it out of reset, you can measure the rx_clk. The clock should be close to what you have configure in the settings.