FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5283 Discussions

Cyclone V Transceiver Native PHY IP Core

S_Healthineers
Beginner
521 Views

Hello, by the Cyclone V Transceiver Native PHY IP Core is the Transceiver Reconfiguration Controller optional ? can i left the Reconfiguration output signals Open and the inputs putted to zero.

 

PS . I don't need  to dynamically change reference clocks, PLL connectivity, and the channel configurations at runtime.

0 Kudos
4 Replies
SengKok_L_Intel
Moderator
203 Views

Hi,

 

Even if there are no reconfigurations at runtime, this still needs to connect the Transceiver Reconfiguration controller to the Native PHY. You can't just leave it open without connecting or put to zero.

 

Regards -SK

S_Healthineers
Beginner
203 Views

 

Thanks for the quick response SK Lim,

 

is it enough if I connect  the transceiver with the reconfiguration controller and control only  the mgmt_clk_clk  and mgmt_rst_reset ? or i have to do also something with the communication interface read/write ?

SengKok_L_Intel
Moderator
203 Views

​Yes, you just need to hook up the signals accordingly, and control only the clk and reset signals will do.

 

 

Regards -SK Lim

 

S_Healthineers
Beginner
203 Views
Reply