DE1-SoC: FT UART starts transmitting invalid data after cable is plugged.

[jrodr29]

I am connecting UART to FPGA through io loaning.

UART_RX data is reaching the FPGA,

but serial data transmitted by FPGA is not going through.

UART is only sending bits after cable is connected, or remote terminal starts session.

[ I have disabled any performance/printf configuration in the preloader ]

[ and confirmed RTL connection int the viewer ]

[The baud rate specified in the FT driver is matched with the terminal as well]

Any hints?

[jrodr29]

One step forward : baudrate must be set up to 115200, and I start getting below data;

now : how to stop it and get the TX for the FPGA ...???

< ---

U-Boot SPL 2013.01.01 (Aug 17 2016 - 15:27:26)

BOARD : Altera SOCFPGA Cyclone V Board

CLOCK: EOSC1 clock 25000 KHz

CLOCK: EOSC2 clock 25000 KHz

CLOCK: F2S_SDR_REF clock 0 KHz

CLOCK: F2S_PER_REF clock 0 KHz

CLOCK: MPU clock 800 MHz

CLOCK: DDR clock 400 MHz

CLOCK: UART clock 100000 KHz

CLOCK: MMC clock 50000 KHz

CLOCK: QSPI clock 400000 KHz

RESET: WARM

-->

INFO : Watchdog enabled

SDRAM: Initializing MMR registers

SDRAM: Calibrating PHY

SEQ.C: Preparing to start memory calibration

SEQ.C: CALIBRATION PASSED

SDRAM: 1024 MiB

ALTERA DWMMC: 0

-->

[Fawaz_Al-Jubori]

Hello, Not clear where are you connecting this UART. Is it connected to HPS? because thats what I can see from the above messages. if it is connected to HPS, then you cannot use any internal source of FPGA to use this UART terminal. usually we have two terminals, one is through UART to HSP, and one through JTAG UART to FPGA. Thanks