De10 standard Clock and speed issue

[CAlex]

Hi,

I'm a little confused on the clock issues, I'm working on Liunx based system with the debug mode.

I created a flag signal that it will flip in 50us.

I posted the signal from the FPGA to the HPS and send it to the GPIO1. So the signal is a HPS side signal.

Then I exported the same FPGA signal to the other GPIO2. The signal then become a FPGA side signal.

I tested the latency of both signals, the latency is around 1-1.5 us.

I assume the latency is duel to avalon mm bridge reading/writing and CPU latency.

But I don't know which is the main issue.

Also I found some resources on clock system of the SOC boards. And as usual I get more confused.

I have the following questions:

1.The hps default settings show that MPU clock is 950Mhz, debug clock is 12.5Mhz, and FPGA clock is 50Mhz.  If I use makefile to generate the userspace program then which clock is used?

2.Do you guys have ways to test how many times one code line use? Or does Cyclone V CPUs have a test code to show a standard tick use for a test code? 

3. If using avalon mm bridge latency is the main issue then can that be reduced or is there another way to let the HPS read the FPGA signals?

4.How can I use a faster clock other than the debug clock?

That's all.

Thank you for your help.

reguards.

[EBERLAZARE_I_Intel]

Hi,

Can I see first your .qsys file to check the settings?

[CAlex]

Hi,

Okey, I sent you the whole project to you but not the C file on the HPS(Linux).

Please inform me if you need that to figure out what's happend.

Meanwhile I can psot some settings for any one else want to solve this question:

                           Fig1.Axi Bridge Setting 

                       Fig2. HPS PLL setting

Fig3. System setting, The top one is the cyclone V HPS hps_0

Looking forward to your reply.

reguards.

[EBERLAZARE_I_Intel]

Hi,

Let me look into it. Please expect delay in my response, thanks.

[EBERLAZARE_I_Intel]

Hi,

When you mentioned "I created a flag signal that it will flip in 50us", does it only have latency issue with 50us? Did you do any other testing?

[CAlex]

Hi,

It is done in the FPGA side, and everything in my userspace code is based on that signal.

So I assume it is the start point flag of my whole userspace system.

The test was done and the signal was complete and stable when I read the GPIO 2 channel by the oscilloscope.

reguards.

[EBERLAZARE_I_Intel]

Hi,

Everything seems normal, do you have the device tree as well? I can take a look there.

[CAlex]

Hi,

I'm using the terasic GHRD device tree but didn't add my IP core on that DTB file.

I just upload the .sof file to the board and test it with makefile.

The attached is the Terasic DTB file.

I hope it would be helpful.

Reguards. 

[EBERLAZARE_I_Intel]

Hi,

Thanks, let me check the files.

[EBERLAZARE_I_Intel]

Hi,

Okay, before we jump to the clocking, how did you boot up your board? Are you using SD Card?

Is there a default image for the terasic board and you changed the HPS IP settings after?

[CAlex]

Hi,

yes Im using sdcard

and yes I use the default image and changed my HPS IP

Reguards.

[EBERLAZARE_I_Intel]

Hi,

Did you re-generate all the boot/Uboot files after changing the HPS IP settings?

[CAlex]

Hi,

no I didn't.

I mainly decreased the HPS settings and uboot boots well on my board.

I can try re-generate the uboot but I think it would make any different.

Reguards.

[EBERLAZARE_I_Intel]

Hi,

From my understanding, the settings are carried over by the handoff folder from Quartus when you build the U-boot, which is why the U-boot need to be regenerated when changing the HPS IP's settings.

Maybe you could use the default image from Terasic and see if using the default differs or seeing the same issue using the default clock settings?

[CAlex]

Good idea, I will have a try.

[EBERLAZARE_I_Intel]

Hi,

Did the result from testing using default image from Terasic differs?

[EBERLAZARE_I_Intel]

Hi,

Any update from your side?

[EBERLAZARE_I_Intel]

Hi,

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