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De10 standard Clock and speed issue

CAlex
New Contributor II
1,430 Views

Hi,

I'm a little confused on the clock issues, I'm working on Liunx based system with the debug mode.

I created a flag signal that it will flip in 50us.

I posted the signal from the FPGA to the HPS and send it to the GPIO1. So the signal is a HPS side signal.

Then I exported the same FPGA signal to the other GPIO2. The signal then become a FPGA side signal.

 

I tested the latency of both signals, the latency is around 1-1.5 us.

I assume the latency is duel to avalon mm bridge reading/writing and CPU latency.

But I don't know which is the main issue.

 

Also I found some resources on clock system of the SOC boards. And as usual I get more confused.

 

I have the following questions:

 

1.The hps default settings show that MPU clock is 950Mhz, debug clock is 12.5Mhz, and FPGA clock is 50Mhz.  If I use makefile to generate the userspace program then which clock is used?

 

2.Do you guys have ways to test how many times one code line use? Or does Cyclone V CPUs have a test code to show a standard tick use for a test code? 

 

3. If using avalon mm bridge latency is the main issue then can that be reduced or is there another way to let the HPS read the FPGA signals?

 

4.How can I use a faster clock other than the debug clock?

 

That's all.

 

Thank you for your help.

 

reguards.

 

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17 Replies
EBERLAZARE_I_Intel
1,404 Views

Hi,


Can I see first your .qsys file to check the settings?


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CAlex
New Contributor II
1,398 Views

Hi,

 

Okey, I sent you the whole project to you but not the C file on the HPS(Linux).

Please inform me if you need that to figure out what's happend.

Meanwhile I can psot some settings for any one else want to solve this question:

CAlex_0-1679535373899.png

                           Fig1.Axi Bridge Setting 

CAlex_1-1679535435556.png

                       Fig2. HPS PLL setting

 

CAlex_2-1679535527769.png

Fig3. System setting, The top one is the cyclone V HPS hps_0

 

Looking forward to your reply.

 

reguards.

 

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EBERLAZARE_I_Intel
1,360 Views

Hi,


Let me look into it. Please expect delay in my response, thanks.


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EBERLAZARE_I_Intel
1,329 Views

Hi,


When you mentioned "I created a flag signal that it will flip in 50us", does it only have latency issue with 50us? Did you do any other testing?


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CAlex
New Contributor II
1,323 Views

Hi,

 

It is done in the FPGA side, and everything in my userspace code is based on that signal.

So I assume it is the start point flag of my whole userspace system.

The test was done and the signal was complete and stable when I read the GPIO 2 channel by the oscilloscope.

 

reguards.

 

 

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EBERLAZARE_I_Intel
1,287 Views

Hi,


Everything seems normal, do you have the device tree as well? I can take a look there.


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CAlex
New Contributor II
1,275 Views

Hi,

 

I'm using the terasic GHRD device tree but didn't add my IP core on that DTB file.

I just upload the .sof file to the board and test it with makefile.

The attached is the Terasic DTB file.

 

I hope it would be helpful.

 

Reguards. 

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EBERLAZARE_I_Intel
1,250 Views

Hi,


Thanks, let me check the files.


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EBERLAZARE_I_Intel
1,224 Views

Hi,


Okay, before we jump to the clocking, how did you boot up your board? Are you using SD Card?


Is there a default image for the terasic board and you changed the HPS IP settings after?


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CAlex
New Contributor II
1,194 Views

Hi,

yes Im using sdcard

and yes I use the default image and changed my HPS IP

 

Reguards.

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EBERLAZARE_I_Intel
1,165 Views

Hi,


Did you re-generate all the boot/Uboot files after changing the HPS IP settings?


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CAlex
New Contributor II
1,162 Views

Hi,

no I didn't.

I mainly decreased the HPS settings and uboot boots well on my board.

I can try re-generate the uboot but I think it would make any different.

 

Reguards.

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EBERLAZARE_I_Intel
1,148 Views

Hi,


From my understanding, the settings are carried over by the handoff folder from Quartus when you build the U-boot, which is why the U-boot need to be regenerated when changing the HPS IP's settings.


Maybe you could use the default image from Terasic and see if using the default differs or seeing the same issue using the default clock settings?


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CAlex
New Contributor II
1,134 Views
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EBERLAZARE_I_Intel
1,073 Views

Hi,


Did the result from testing using default image from Terasic differs?


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EBERLAZARE_I_Intel
1,046 Views

Hi,


Any update from your side?


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EBERLAZARE_I_Intel
1,014 Views

Hi,


I hope that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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