Does the logic inside flash memory devices require a power down after each WRITE operation?

[Chloé_Russell]

Hello, 

After WRITE operations (program or erase sector) to the Flash Memory, it does not respond to any instruction during power-up except READ STATUS REGISTER, I have reset the circuit and the device remains in lock mode. I have to power down the chip to unlock the memory and get correct values (previously written) back from the EPCQL. I'm wondering if it is a normal behave of Flash memories or am I missing something..

The write bytes/erase sector command sequecing is respected and the data read back after power down being as expected. Any help or points in a direction would be much appreciated. Thank you in advance

[AnandRaj_S_Intel]

Hi,

1. The status register can be read continuously and at anytime, including during a write or erase operations.
2.  The EPCS/EPCQ/EPCAL device is a flash memory device that can store configuration data that we use for FPGA configuration purpose after power cycle.
3. If the read bytes operation is shifted in while a write or erase cycle is in progress, the operation is not executed and does not affect the write or erase cycle in progress.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand

[Chloé_Russell]

Hi Anand,

Thank you for your reply.

1. I am trying to access in read and write my EPCQL-1024 using the Quartus Prime version 16.0. I have the Altera Serial Flash Controller I configured in QUAD mode connected from its avl_csr and avl_mem to the NIOSII.
2. As the NIOSII is booting from an onchip memory I think that it's no need to program the flash memory with jic file. Tell me please if I'm missing something. I have tried to access in read and write the EPCQL registers (STATUS, Device ID) and the controller registers FLASH_ISR, or FLASH_IMR, protect sectors also and it have been successful.
3. Here lies my problem: after WRITE operations (erase sector or write bytes), the device does not respond to any instruction except the READ STATUS REGISTER, although the read status register value indicates that there is no erase or write cycle in progress (the WIP bit is 0 so the write operation is completed). I need to power off the chip then power on and reload my .sof to get values back from my EPCQL and the data read back after power down being as expected.

Kindly, check the attached file given here below, you will find screenshots of my system to show you connections I have made and running results. I’m wondering if the logic inside flash memory devices requires a power down after each WRITE operation.

Your reply will be appreciated, thank you in advance. 

Best Regards,

CR

[AnandRaj_S_Intel]

Hi CR,

Apologies,

Just an update I have replicated the scenario, we will get back on this.

In case if you have found the solution/work around can you please share the solution.

Best Regards

Anand

[Chloé_Russell]

Hello Arnaud, Thank you for taking the time to reply me. I’m trying to resolve the issue by programming my flash using another methods: 1- Although my purpose is to program my flash with an executable application and I do not need to program the FPGA configuration into it but I’ve tried to program my flash using JIC file , I generated the JIC using only SOF file, after resetting the board , the FPGA has been successfully configured but I can’t run nothing with the Flash because it was fully written by the JIC configuration. For this, my question is : should the EPCQ size be faithful to the qsys system configuration (I’m using a board that has flash EPCQ-L 1024 and for specific reasons I’m using a flash controller for EPCQ-L256)? 2- I’ve tried to program my flash using the Nios II flash programmer with an executable software ELF file, but I found the following error: 3- I’ve tried also to use the Nios II shell commands with the debug option but I’ve got errors.. Kindly, check the attached file given here below I’m waiting for your directions, thank you. Best regards, CR