Doubts about the download of the configuration of Cyclone 10 LP

[PedroJServian]

Hi colleagues,

I am a newbie FPGA programmer of Cyclone 10 LP. I programmed MAX10 FPGAs but for my actual design I needed to migrate to 10CL040YF484I7G device.

When I programmed for the MAX10 device, I designed my .bdf, then I compiled and it generated two files .sof and .pof. The .sof file was for SRAM volatile so when I switched off the power supply the program needed to be downloaded again with the JTAG. However, with the .pof file, the FPGA remained loading the program I once loaded the first time after the power off. So as far as I'm concerned, the .pof file loads the program in the internal flash and then, I boots the FPGA with the program in the flash after a power off happened. 

What I'm struggling now is with this Cyclone 10 LP FPGA is that it seems that doesn't have internal flash memory so I wanted to know what are the strategies that able me to download the compiled output program to the FPGA and keep it booting to the FPGA even if the power supply of the FPGA is off. Is that possible? Do I need to put an external flash memory? Is there an option when you compile that takes logic elements of the FPGA to make a flash memory and load the output program as desired? In summary, I just want to download a program to this FPGA and that this FPGA keep the program when is shut down (only change the program when I reprogram it via JTAG).

Sorry if this sound as a very dummie question, I am a new developer and I need help with this hardware issues. Thank you in advance, have a nice day.

Regards,

Pedro

[FvM]

Hi,
you need an external configuration memory device. Active serial (AS) scheme is most simple, flash can be programmed through existing JTAG. 10CL040 has maximal 9 MBit configuration image, respectively 16 MBit serial flash like EPCS16A or compatible industry standard device can hold it. Larger flash if you target to in-system upgrade or additionally want to store Nios Software.

[PedroJServian]

Hi @FvM ,

What do you refer to configuration image? The file in .sop or .pof format. I have just compiled the previous project I had in my MAX10 FPGA and those files .sof and .pof only required 716KB and 315KB respectively.

However, I just took that project, I changed the device and the compilations I got gave me that those files require 1152KB(.sof) and 2049KB. I thought that maybe the program image was the .jic file that I converted but it required 16000KB. I can assure you that the design is not very complex so it can't be that it exceeded the 9Mbit of maximum image you told. 

Where can I found the weight of the configuration image you told so I could size the correct memory of the external flash?

Thank you!!

[FvM · Accepted solution]

I'm referring to maximal binary image size, e.g. .rbf file, it's specified in device handbook configuration chapter. An actual design will be usually smaller but flash should be chosen for maximal size.
When using suggested flash programming through JTAG, you'll convert design .sof to .jic with Programming File Converter tool.

[PedroJServian]

Hi @FvM 

Than you againt for your help. I feel a little bit lost with this part of hardware.

Have a nice day

Pedro