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Dual Configuration Intel FPGA IP Core


I'm sorry, I can't reply to your answer. Is this link: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Dual-Configuration-Intel-FPGA-IP-Core/m-p/1514837.

I don't know how to reply, click the reply button, there is no response.

About using MAX10M08SAU169I7G to implement remote update function.
1. How should I connect the config_sel pin in my schematic?
2. I try to change state1: write=1; address= 0x01; writedata= 0x01; , but again, you can't switch to factory image.
3. I read read=1; address= 0x03; , but avmm_rcv_readdata is always 0. I can't detect the busy signal becoming high.

I don't know how to correctly use Dual Configuration Intel FPGA IP Core, can you write a design program for me?

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Hi Huan,

For MAX 10’s config_sel: This is a dual-purpose pin. Use this pin to choose the configuration image in the dual-configuration images mode.

If the CONFIG_SEL pin is set to low, the first configuration image is configuration image 0. If the CONFIG_SEL pin is set to high, the first configuration image is configuration image 1.

This pin is read before user mode and before the nSTATUS pin is asserted.

More info can refer this document: https://www.intel.com/content/www/us/en/docs/programmable/683232/current/configuration-jtag-pins.html

According to your description: I doubt the correctness of your use of IP because of the no response of readdata. Do u try to read back the data in 0x01?

Here is a demo of RSU of MAX10. You can refer it: https://www.intel.com/content/www/us/en/design-example/714746/max-10-i2c-remote-system-update-example.html

Best regards,


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