E-tile automatic adaptation issues

[alexforencich]

I am attempting to bring up a 10G Ethernet link on a Stratix 10 DX development kit via the E-tile. I have managed to get a link, but so far only with the help of the system console to load the 10G-NRZ settings. It appears that the RX adaptation settings are not being updated from the defaults, despite selecting "Enable adaptation load soft IP".

The IP parameter editor does display the following info message (it does not appear to be an error or warning):

Info: mac.alt_ehipc3_0: Enabling both parameters "rcfg_enable" (Enable dynamic reconfiguration) and "set_csr_soft_logic_enable" (Enable control and status registers) in PHY IP is required when Adaptation Load feature is enabled.

However, I cannot find the mentioned settings in the parameter editor to see if they are set correctly. I can see them if I create an E-tile native PHY core (under the dynamic reconfiguration tab), but that tab is missing for the E-tile hard IP core.

[alexforencich]

Some additional details: I have tried both "single 10GE/25GE" and "1 to 4 10GE/25GE with optional RS-FEC" and have so far seen the same results. RS-FEC and AN are disabled, with AN enabled not only do I not get a link, but the system console does not want to talk to the MAC.  Under PMA adaptation I have selected NRZ_10Gbps, which sets GS1 = 2, GS2 = 1, RF_B1 = 5 fixed, RF_B0 = 1 fixed. 

After loading the design on the FPGA and connecting to it with the system console, the MAC reports HI-BER and the receiver adaptation settings are GS1 = 0 adaptive, GS2 = 0 adaptive, RF_B1 = 0 adaptive, RF_B0 = 0 adaptive.  If I select "10G-NRZ" on the MAC and click apply, HI-BER goes away, the NIC reports that the link is up, and the receiver adaptation settings are GS1 = 0 fixed, GS2 = 1 fixed, RF_B1 = 5 fixed, RF_B0 = 1 fixed.  So it's not quite the same as what the PMA adaptation tab in the parameter editor lists, but the connection works. 

The question is why: is there something that I need to do to trigger the adaptation load soft IP to do its thing and configure the transceiver with the proper settings?  I have not found anything in the documentation about this. 

[Deshi_Intel · Accepted solution]

HI,

If you want to learn how Etile PMA adaptation flow works, then pls checkout below user guide (page 210, 211)

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_etile_xcvr_phy.pdf

Else you want to see how E-tile Hard IP control the adaptation flow, kindly refer to page 109 of below doc

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-etile-hip-ethernet.pdf

Like wise, you can also checkout E-tile hard IP example design directly for the design implementation example

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-etile-hip-ethernet.pdf

Thanks.

Regards,

dlim

[alexforencich]

Ok, I was under the impression that this was supposed to be automatic - just check the box, and the soft IP takes care of the rest.  You're telling me that I have to implement the flowchart in figure 117 in that first link myself?  That's rather lame, but I suppose at least the settings are stored inside the core so I just need to tell it what to do. 

[Deshi_Intel]

HI,

Unfortunately there is that case here. PMA adaptation process flow is not automatic.

Yes, you can refer to flowchart or the E-tile HardIP example design to learn how it control the adaptation flow.

Thanks.

Regards,

dlim

[alexforencich]

Alright, I was able to make this work by writing a state machine that implements the operations listed in section 8.2.13 on page 211 of the E-tile PHY user guide.  Unfortunately, I don't know what to wait for before starting the sequence, right now I just wait 65k clock cycles.  Not a particularly clean solution, but I suppose it will be sufficient at least for the time being.  The documentation for this stuff is really quite terrible.