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EPCS Active serial Configuration on Cyclone IV GX FPGA Development Kit

Honored Contributor II


i'm intrested to know if there is a way of checking the AS configuration as described in "Configuration and Remote System Upgrades in Cyclone IV Devices" (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf - figure 8-2) on the "Cyclone IV GX FPGA Development Kit" (http://www.altera.com/products/devkits/altera/kit-cyclone-iv-gx.html). 

I can see the MAX II CPLD is the device interfacing the serial configuration device (EPCS128 decive), is there a way to bypass it to check the programming without the CPLD in the loop? 

where does the DATA[0], DCLK, nCSO and ASDO ports from the Cyclone device go to? 



thank you 



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