Hello .. A Newbie to Intel here.
I am beginning to use Quartus 18.1 to develop on the Cyclone 10GX evaluation board. I can compile and download small test code to the FPGA through the JTAG port using a USB Blaster (Rev c) device. No problem with this; the JTAG seems to be working fine.
However, when trying to start the Board Test System supplied with the dev package I receive the message "Error when scanning hardware - No devices!".
The reference design as supplied was built using Quartus version 18.104.22.168 so I rebuilt the bts_config using 18.1 but the same error ..
Any help from you guys out there ? Thanks in advance for any tips here.
Thank you for your reply!
Yes I also thought that might influence the initial link up between the application running on the PC and the FPGA board but then I saw that the 17.1 revision of Quartus Prime doesn't support the Cyclone 10GX device.
However, I did download the 17.1 version of Quartus and installed it and get exactly the same result. I'm confident now that the JTAG interface is intact but have notice that when I open the System console I receive the following error which might be a symptom of the same problem that the Board Test System is having accessing the evaluation board ..
May 16, 2019 11:57:08 AM com.altera.debug.core
SEVERE: Unable to scan chain: HARDWARE_DISABLED
Unable to scan chain: HARDWARE_DISABLED
at com.altera.systemconsole.internal.plugin.jtag.aji.AJICable.getDevices0(Native Method)
I'm still in trouble !! Any further help or clarification would be appreciated.
I now realize that the HARDWARE_DISABLED error occurring in System Console initialization is associated with a Blaster II USB port I had installed and that cannot operate under the 64-bit OS. I had inadvertently created this port when installing the working USB Blaster (Rev c) download cable driver. So this has nothing to do with the problem I am having with the Board Test System.
So the problem continues, full functionality of JTAG interface, all path and environment variables correctly point to their respective resources, Can run code downloaded to the target Cyclone 10GX evaluation board, but cannot connect using the Board Test System executable as shipped with the kit resources. The wording of the evaluation kit User Guide tells me that the Quartus version must be _later_ than that used to generate the development kit .sof ("... you should install the latest Intel Quartus Prime software that can support the silicon on the development kit" ...).
From the System Console, when running 'get_default_master' from the tcl console command line I receive the following reply which I believe tends to support my idea that the JTAG and socket server on the FPGA are working correctly. Is this a reasonable deduction ?
/devices/10CX220Y@2#USB-0/(link)/JTAG/(70:34 v3 #0)/nios2_0
Any ideas as to what I may try to further diagnose this problem ??
Thanks in advance for any insights !