FFT Intel FPGA IP

[binfu1]

When I use FFT Intel FPGA IP (version 19.1), the simulation results of fft is correct (compared with python calculate results). Then I assert inverse signal to calculate ifft, the results is incorrect. Note that the configuration of the IP is as follows. Can you tell me why the error happens, and how to solve this problem, thanks.

[CheePin_C_Intel]

Hi,

Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.

[CheePin_C_Intel]

Hi,

I understand you’re experiencing unexpected results with the iFFT output from the Intel FPGA FFT IP. To help ensure we’re aligned and to assist you effectively, could you please share the following details:

1. The specific FPGA device and Quartus version you’re using.

2. A simple simulation setup in QuestaSim that replicates the issue, along with the detailed steps you followed.

3. The expected (golden) results and a brief explanation of the discrepancy you’re observing.

4. Just wonder if similar issue observed if you are using single direction iFFT.

This information will help me better understand the context and investigate further.

Please let me know if you have any concerns or need clarification. Thank you.

Best regards,

Chee Pin

[binfu1]

Hi,

    Thanks for your reply, the feedback of your requests are as follows:

    1.The FPGA device is Agilex7: AGIB027R29A1E2VR0, Quartus version is Quartus-pro-24.3.0.212.

    2.The simulator is vcsmx, following the standard simulation steps.

    3.First I simulate the forward FFT, the input data is shown as Fig.1, and the simulation result is shown as Fig.2. After digit-reverse, the result is shown as Fig.3. The calculation result of python is shown as Fig.4, and we can see the results of calculation and simulation are consistent. Then I simply assert the inverse signal of FFT Intel FPGA IP, the input data is same as before, the simulation result is shown as Fig.5 (after digit-reverse), and the calculation results of python is shown as Fig.6. we can see the results are inconsistent. I have tried the Variable Size FFT Intel FPGA IP for the same calculation, the result is shown in Fig.7 (after bit-reverse), and we can see the results are consistent. As a result, I confirm the calculation result of python is correct, and the simulation result of Intel FPGA FFT IP is wrong.

    4.I have tried set direction as reverse only, the results is same (wrong).

Best regards