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FIFO based module implementation Error. Results not as expected, using Quartus Prime Software and vJTAG implementation method.

New Contributor I

The module I’m trying to implement works like a FIFO but with a slightly different functionality.

Say I have lots of colored balls, which I’m putting it into the tube that is like the FIFO memory of the module.


1.   Every time there is an update signal (udr) a new ball gets added into the tube (writing)

2.   Now if the color of the ball that just entered the tube is blue, then reading begins

3.   The reading and writing takes place simultaneously and the reading stops once the blue ball is out. Writing keeps on happening whenever there is an update signal.

4.   Now if a second blue ball enters the tube, reading starts again until the blue ball is out

5.   So I have two flags F1 and F2. F1 keeps track of the number of blue balls in the pipe, and the second flag keeps track of whether there is a reading taking place.


Code Logic –

1.   At udr, if the write counter has not reached max, I want the writing to take place and the address to be continued from wherever it stopped last time. (eg. If it stopped at 13, it continues with write address as 14). If, however the max limit has reached I want the counter to reset and write it into the beginning (as a normal FIFO). I have kept the number of lines large enough so that overwriting would never take place without a read already happening.

2.   If the data coming in is the reset line (which is basically all “0”) then F1 will be incremented by 1.

3.   If F1 is not zero, then reading begins only if a reading is not already taking place (meaning F2 = 0). And then it turns F2 to 1 meaning a read is taking place. Now if the read counter is at the limit then the read counter resets and reads from 0, else it continues reading from wherever it left off, (eg. If it stopped at 13, it continues with reading from 14). Read enable is turned on and read counter is incremented unitarily. Each read has a time delay of 10 clock pulses.

4.   Now when the reading is taking place, it may receive a done signal from the receiving end, if the receiving end reads a reset line. If it gets a done signal, then F1 will be deducted by 1 to signify that 1 read has taken place. The module then checks if the F1 is zero, if it is still not that means another reset line was written into the fifo memory when the reading was taking place, so the reading continues, until F1 is 0 which means there is no more reading that needs to take place. So it stops reading and turn F2 = 0 (false)


This is what I want to implement and the code is attached herewith. However, I’m not able to get any reading on the output. Please advise regarding the same.


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3 Replies
New Contributor III

Are you simply simulating this code? Or are you trying to synthesise this code and put it into a device? Does your simulation work?


The code, as is, is not going to do some of the things your comments indicate you want it to do - not in a device anyway. You cannot us #10 to delay by 10 'timesteps' (clock cycles?). These delays are for simulation only.


I recommend you code everything with nonblocking statements. I can see you've suggested you need to keep the order of statements. However, they're doing as you want. Change them all to nonblocking and make sure the simulation works. Remember to only update each register once per conditional branch (if / else). Coded cleanly you can do everything with the nonblocking operator - certainly everything you're trying to do here.


I see a number of other bits of the code that suggest to me that you've not simulated this - I could be wrong. Make sure the simulation behaves before proceeding to a device.




New Contributor I

No actually, I intend to synthesis this code to put into a device. I couldn't simulate it because the input actually comes from vJTAG server communication meaning from a separate python code, so I'm not sure how to simulate that in Quartus alone. The results I'm referring to is what I observe after synthesizing it into the device.

If the time delay can't be simulated by "#10" alone how can I write the Verilog code to pause/delay for 10 clock cycles? Furthermore if I use a display command ($display) where would I see the results I'm trying to display?

The non-blocking statements I avoided because I was of the understanding that non blocking statements are executed without an order, whereas blocking statements ensure that the previous statement has been executed before moving to the next. Kindly elaborate as to why non blocking statements would not be an issue here.

Also please help highlight any other part of the code which is not going to do some of the things my comments indicates I want it to do.


Thank you for your help and response!



New Contributor III

To pause for 10 clock cycles you need to implement a counter to count them. This will need at least 4 flip-flops. You can then continue to do whatever next.


$display is only used for simulation. It has no effect or use in synthesisable code.


Blocking vs non-blocking is a very common issue, frequently misunderstood. You always need to consider what the gates are going to look like when writing your code. This will help you understand what values each storage element - flip-flop - will hold after each clock cycle.

Have a look at: