Facing some placement issue in F-tile of agilix board, while trying to compile Ethernet and JESD204C

SreekanthB · ‎04-29-2024

I am trying to compile a design in Quartus Prime 22.3 for Intel Agilex board. the design has both the JESD and Ethernet IPs. while trying to compile the design, It is trowing so many errors. Basically telling me that the F-tile doesn't have enough resources init.

But the board I am using have 2 F-tiles in it, I am thinking that the constraints that i gave are not correct. Here I am attaching the head and tail of the errors.

Thanks in advance.

Harshx · ‎04-29-2024

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case related to JESD & ETH and get back to you soon once I have any finding.

Meanwhile can I check with you on following details:

Quartus Device name you are using? (Assignment -> Device)
Are you able to share the design? (Archived)

Thanks for your patience.

Best regards,

HarshX

SreekanthB · ‎04-29-2024

Hey Hii.

Thanks for responding, the board I am using is AGFB027R24C2E2VR2.

Sorry I cant share my design but here is the .qsf of the design.

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2022 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 22.3.0 Build 104 09/14/2022 SC Pro Edition
# Date created = 12:08:55 December 16, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ghrd_agfb027r24c2e2vr0_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #

# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:25:44 NOVEMBER 24, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "22.3.0 Pro Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DESIGN_ASSISTANT_INCLUDE_IP_BLOCKS ON
set_global_assignment -name FLOW_DISABLE_ASSEMBLER OFF

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_CY48 -to FBR_CLK_100M
set_location_assignment PIN_BC49 -to FTILE_REFCLK
set_location_assignment PIN_BE49 -to "FTILE_REFCLK(n)"
set_location_assignment PIN_CY32 -to FTILE_OUTCLK
set_location_assignment PIN_DA33 -to "FTILE_OUTCLK(n)"
set_location_assignment PIN_CT42 -to TOD_REFCLK
set_location_assignment PIN_CR43 -to "TOD_REFCLK(n)"
set_location_assignment PIN_BG55 -to FTILE_RX_SERIAL[0]
set_location_assignment PIN_BH54 -to FTILE_RX_SERIAL_N[0]
set_location_assignment PIN_BK52 -to FTILE_TX_SERIAL[0] -comment "PIN_BK52 as per schematic"
set_location_assignment PIN_BJ51 -to FTILE_TX_SERIAL_N[0] -comment "PIN_BJ51 as per schematic"
set_location_assignment PIN_DF46 -to AG_FBR_RSTN
set_location_assignment PIN_Y42 -to MASTER_TOD_PPS
set_location_assignment PIN_U5 -to DDR4_HPS_RCLK
set_location_assignment PIN_T6 -to "DDR4_HPS_RCLK(n)"
set_location_assignment PIN_AH10 -to HPS_OSC_CLK
set_location_assignment PIN_L7 -to DDR4_HPS_MEM_CK[0]
set_location_assignment PIN_M8 -to DDR4_HPS_MEM_CK_N[0]
set_location_assignment PIN_U11 -to DDR4_HPS_MEM_A[0]
set_location_assignment PIN_T12 -to DDR4_HPS_MEM_A[1]
set_location_assignment PIN_W11 -to DDR4_HPS_MEM_A[2]
set_location_assignment PIN_Y12 -to DDR4_HPS_MEM_A[3]
set_location_assignment PIN_U9 -to DDR4_HPS_MEM_A[4]
set_location_assignment PIN_T10 -to DDR4_HPS_MEM_A[5]
set_location_assignment PIN_W9 -to DDR4_HPS_MEM_A[6]
set_location_assignment PIN_Y10 -to DDR4_HPS_MEM_A[7]
set_location_assignment PIN_U7 -to DDR4_HPS_MEM_A[8]
set_location_assignment PIN_T8 -to DDR4_HPS_MEM_A[9]
set_location_assignment PIN_W7 -to DDR4_HPS_MEM_A[10]
set_location_assignment PIN_Y8 -to DDR4_HPS_MEM_A[11]
set_location_assignment PIN_Y6 -to DDR4_HPS_MEM_A[12]
set_location_assignment PIN_U3 -to DDR4_HPS_MEM_A[13]
set_location_assignment PIN_T4 -to DDR4_HPS_MEM_A[14]
set_location_assignment PIN_W3 -to DDR4_HPS_MEM_A[15]
set_location_assignment PIN_Y4 -to DDR4_HPS_MEM_A[16]
set_location_assignment PIN_P12 -to DDR4_HPS_MEM_ACT_N[0]
set_location_assignment PIN_T2 -to DDR4_HPS_MEM_BA[0]
set_location_assignment PIN_W1 -to DDR4_HPS_MEM_BA[1]
set_location_assignment PIN_Y2 -to DDR4_HPS_MEM_BG[0]
set_location_assignment PIN_R9 -to DDR4_HPS_MEM_CKE[0]
set_location_assignment PIN_R11 -to DDR4_HPS_MEM_CS_N[0]
set_location_assignment PIN_R7 -to DDR4_HPS_MEM_CS_N[1]
set_location_assignment PIN_L9 -to DDR4_HPS_MEM_ODT[0]
set_location_assignment PIN_M12 -to DDR4_HPS_MEM_RESET_N[0]
set_location_assignment PIN_P8 -to DDR4_HPS_MEM_PAR[0]
set_location_assignment PIN_W5 -to DDR4_HPS_RZQ
set_location_assignment PIN_U1 -to DDR4_HPS_MEM_ALERT_N[0]
set_location_assignment PIN_L3 -to DDR4_HPS_MEM_DQS[0]
set_location_assignment PIN_G3 -to DDR4_HPS_MEM_DQS[1]
set_location_assignment PIN_U15 -to DDR4_HPS_MEM_DQS[2]
set_location_assignment PIN_L15 -to DDR4_HPS_MEM_DQS[3]
set_location_assignment PIN_A7 -to DDR4_HPS_MEM_DQS[4]
set_location_assignment PIN_G9 -to DDR4_HPS_MEM_DQS[5]
set_location_assignment PIN_L21 -to DDR4_HPS_MEM_DQS[6]
set_location_assignment PIN_U21 -to DDR4_HPS_MEM_DQS[7]
set_location_assignment PIN_AA5 -to DDR4_HPS_MEM_DQS[8]
set_location_assignment PIN_M4 -to DDR4_HPS_MEM_DQS_N[0]
set_location_assignment PIN_F4 -to DDR4_HPS_MEM_DQS_N[1]
set_location_assignment PIN_T16 -to DDR4_HPS_MEM_DQS_N[2]
set_location_assignment PIN_M16 -to DDR4_HPS_MEM_DQS_N[3]
set_location_assignment PIN_B8 -to DDR4_HPS_MEM_DQS_N[4]
set_location_assignment PIN_F10 -to DDR4_HPS_MEM_DQS_N[5]
set_location_assignment PIN_M22 -to DDR4_HPS_MEM_DQS_N[6]
set_location_assignment PIN_T22 -to DDR4_HPS_MEM_DQS_N[7]
set_location_assignment PIN_AB6 -to DDR4_HPS_MEM_DQS_N[8]
set_location_assignment PIN_L1 -to DDR4_HPS_MEM_DQ[0]
set_location_assignment PIN_M6 -to DDR4_HPS_MEM_DQ[1]
set_location_assignment PIN_R1 -to DDR4_HPS_MEM_DQ[2]
set_location_assignment PIN_P2 -to DDR4_HPS_MEM_DQ[3]
set_location_assignment PIN_R5 -to DDR4_HPS_MEM_DQ[4]
set_location_assignment PIN_M2 -to DDR4_HPS_MEM_DQ[5]
set_location_assignment PIN_P6 -to DDR4_HPS_MEM_DQ[6]
set_location_assignment PIN_L5 -to DDR4_HPS_MEM_DQ[7]
set_location_assignment PIN_G5 -to DDR4_HPS_MEM_DQ[8]
set_location_assignment PIN_F6 -to DDR4_HPS_MEM_DQ[9]
set_location_assignment PIN_G1 -to DDR4_HPS_MEM_DQ[10]
set_location_assignment PIN_J5 -to DDR4_HPS_MEM_DQ[11]
set_location_assignment PIN_F2 -to DDR4_HPS_MEM_DQ[12]
set_location_assignment PIN_K2 -to DDR4_HPS_MEM_DQ[13]
set_location_assignment PIN_J1 -to DDR4_HPS_MEM_DQ[14]
set_location_assignment PIN_K6 -to DDR4_HPS_MEM_DQ[15]
set_location_assignment PIN_U13 -to DDR4_HPS_MEM_DQ[16]
set_location_assignment PIN_T18 -to DDR4_HPS_MEM_DQ[17]
set_location_assignment PIN_Y14 -to DDR4_HPS_MEM_DQ[18]
set_location_assignment PIN_U17 -to DDR4_HPS_MEM_DQ[19]
set_location_assignment PIN_W13 -to DDR4_HPS_MEM_DQ[20]
set_location_assignment PIN_Y18 -to DDR4_HPS_MEM_DQ[21]
set_location_assignment PIN_T14 -to DDR4_HPS_MEM_DQ[22]
set_location_assignment PIN_W17 -to DDR4_HPS_MEM_DQ[23]
set_location_assignment PIN_M18 -to DDR4_HPS_MEM_DQ[24]
set_location_assignment PIN_L17 -to DDR4_HPS_MEM_DQ[25]
set_location_assignment PIN_R17 -to DDR4_HPS_MEM_DQ[26]
set_location_assignment PIN_L13 -to DDR4_HPS_MEM_DQ[27]
set_location_assignment PIN_M14 -to DDR4_HPS_MEM_DQ[28]
set_location_assignment PIN_R13 -to DDR4_HPS_MEM_DQ[29]
set_location_assignment PIN_P18 -to DDR4_HPS_MEM_DQ[30]
set_location_assignment PIN_P14 -to DDR4_HPS_MEM_DQ[31]
set_location_assignment PIN_D6 -to DDR4_HPS_MEM_DQ[32]
set_location_assignment PIN_E5 -to DDR4_HPS_MEM_DQ[33]
set_location_assignment PIN_E9 -to DDR4_HPS_MEM_DQ[34]
set_location_assignment PIN_C5 -to DDR4_HPS_MEM_DQ[35]
set_location_assignment PIN_D10 -to DDR4_HPS_MEM_DQ[36]
set_location_assignment PIN_B6 -to DDR4_HPS_MEM_DQ[37]
set_location_assignment PIN_B10 -to DDR4_HPS_MEM_DQ[38]
set_location_assignment PIN_A9 -to DDR4_HPS_MEM_DQ[39]
set_location_assignment PIN_F12 -to DDR4_HPS_MEM_DQ[40]
set_location_assignment PIN_J11 -to DDR4_HPS_MEM_DQ[41]
set_location_assignment PIN_G7 -to DDR4_HPS_MEM_DQ[42]
set_location_assignment PIN_K8 -to DDR4_HPS_MEM_DQ[43]
set_location_assignment PIN_F8 -to DDR4_HPS_MEM_DQ[44]
set_location_assignment PIN_G11 -to DDR4_HPS_MEM_DQ[45]
set_location_assignment PIN_J7 -to DDR4_HPS_MEM_DQ[46]
set_location_assignment PIN_K12 -to DDR4_HPS_MEM_DQ[47]
set_location_assignment PIN_R19 -to DDR4_HPS_MEM_DQ[48]
set_location_assignment PIN_P20 -to DDR4_HPS_MEM_DQ[49]
set_location_assignment PIN_M20 -to DDR4_HPS_MEM_DQ[50]
set_location_assignment PIN_L19 -to DDR4_HPS_MEM_DQ[51]
set_location_assignment PIN_L23 -to DDR4_HPS_MEM_DQ[52]
set_location_assignment PIN_R23 -to DDR4_HPS_MEM_DQ[53]
set_location_assignment PIN_P24 -to DDR4_HPS_MEM_DQ[54]
set_location_assignment PIN_M24 -to DDR4_HPS_MEM_DQ[55]
set_location_assignment PIN_W19 -to DDR4_HPS_MEM_DQ[56]
set_location_assignment PIN_T20 -to DDR4_HPS_MEM_DQ[57]
set_location_assignment PIN_W23 -to DDR4_HPS_MEM_DQ[58]
set_location_assignment PIN_U23 -to DDR4_HPS_MEM_DQ[59]
set_location_assignment PIN_Y24 -to DDR4_HPS_MEM_DQ[60]
set_location_assignment PIN_T24 -to DDR4_HPS_MEM_DQ[61]
set_location_assignment PIN_Y20 -to DDR4_HPS_MEM_DQ[62]
set_location_assignment PIN_U19 -to DDR4_HPS_MEM_DQ[63]
set_location_assignment PIN_AA1 -to DDR4_HPS_MEM_DQ[64]
set_location_assignment PIN_AD2 -to DDR4_HPS_MEM_DQ[65]
set_location_assignment PIN_AD6 -to DDR4_HPS_MEM_DQ[66]
set_location_assignment PIN_AE7 -to DDR4_HPS_MEM_DQ[67]
set_location_assignment PIN_AE1 -to DDR4_HPS_MEM_DQ[68]
set_location_assignment PIN_AB8 -to DDR4_HPS_MEM_DQ[69]
set_location_assignment PIN_AA7 -to DDR4_HPS_MEM_DQ[70]
set_location_assignment PIN_AB2 -to DDR4_HPS_MEM_DQ[71]
set_location_assignment PIN_R3 -to DDR4_HPS_MEM_DBI[0]
set_location_assignment PIN_J3 -to DDR4_HPS_MEM_DBI[1]
set_location_assignment PIN_W15 -to DDR4_HPS_MEM_DBI[2]
set_location_assignment PIN_R15 -to DDR4_HPS_MEM_DBI[3]
set_location_assignment PIN_E7 -to DDR4_HPS_MEM_DBI[4]
set_location_assignment PIN_J9 -to DDR4_HPS_MEM_DBI[5]
set_location_assignment PIN_R21 -to DDR4_HPS_MEM_DBI[6]
set_location_assignment PIN_W21 -to DDR4_HPS_MEM_DBI[7]
set_location_assignment PIN_AA3 -to DDR4_HPS_MEM_DBI[8]
set_location_assignment PIN_AC15 -to HPS_SDMMC_CCLK
set_location_assignment PIN_AL15 -to HPS_SDMMC_CMD
set_location_assignment PIN_AJ11 -to HPS_SDMMC_D0
set_location_assignment PIN_AM16 -to HPS_SDMMC_D1
set_location_assignment PIN_AH12 -to HPS_SDMMC_D2
set_location_assignment PIN_AN15 -to HPS_SDMMC_D3
set_location_assignment PIN_AG13 -to HPS_SDMMC_D4
set_location_assignment PIN_AP16 -to HPS_SDMMC_D5
set_location_assignment PIN_AF14 -to HPS_SDMMC_D6
set_location_assignment PIN_AT16 -to HPS_SDMMC_D7
set_location_assignment PIN_AF10 -to HPS_EMAC1_TX_CLK
set_location_assignment PIN_AU11 -to HPS_EMAC1_TX_CTL
set_location_assignment PIN_AG7 -to HPS_EMAC1_TXD0
set_location_assignment PIN_AP12 -to HPS_EMAC1_TXD1
set_location_assignment PIN_AD12 -to HPS_EMAC1_TXD2
set_location_assignment PIN_AM12 -to HPS_EMAC1_TXD3
set_location_assignment PIN_AF8 -to HPS_EMAC1_RX_CLK
set_location_assignment PIN_AT12 -to HPS_EMAC1_RX_CTL
set_location_assignment PIN_AC13 -to HPS_EMAC1_RXD0
set_location_assignment PIN_AN11 -to HPS_EMAC1_RXD1
set_location_assignment PIN_AD10 -to HPS_EMAC1_RXD2
set_location_assignment PIN_AL11 -to HPS_EMAC1_RXD3
set_location_assignment PIN_AB10 -to HPS_EMAC1_MDIO
set_location_assignment PIN_AJ13 -to HPS_EMAC1_MDC
set_location_assignment PIN_AC11 -to HPS_I2C1_SDA
set_location_assignment PIN_AT10 -to HPS_I2C1_SCL
set_location_assignment PIN_AB14 -to HPS_SPIM0_CLK
set_location_assignment PIN_AH14 -to HPS_SPIM0_MOSI
set_location_assignment PIN_AB12 -to HPS_SPIM0_MISO
set_location_assignment PIN_AJ9 -to HPS_SPIM0_SS0_N
set_location_assignment PIN_AG9 -to HPS_SPIM1_CLK
set_location_assignment PIN_AT14 -to HPS_SPIM1_MOSI
set_location_assignment PIN_AF12 -to HPS_SPIM1_MISO
set_location_assignment PIN_AU13 -to HPS_SPIM1_SS0_N
set_location_assignment PIN_AP14 -to HPS_SPIM1_SS1_N
set_location_assignment PIN_AD8 -to HPS_UART1_TX
set_location_assignment PIN_AP10 -to HPS_UART1_RX
set_location_assignment PIN_AU15 -to HPS_GPIO0_IO11
set_location_assignment PIN_AJ7 -to HPS_GPIO0_IO12
set_location_assignment PIN_AL13 -to HPS_GPIO0_IO13
set_location_assignment PIN_AH8 -to HPS_GPIO0_IO14
set_location_assignment PIN_AM14 -to HPS_GPIO0_IO15
set_location_assignment PIN_AD14 -to HPS_GPIO0_IO16
set_location_assignment PIN_AN13 -to HPS_GPIO0_IO17
set_location_assignment PIN_AG11 -to HPS_GPIO0_IO18
set_location_assignment PIN_AC9 -to HPS_GPIO1_IO16
set_location_assignment PIN_AM10 -to HPS_GPIO1_IO17

# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON

# Compiler Assignments
# ====================
set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE WITH MAXIMUM PLACEMENT EFFORT"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY ghrd_agilex_top
set_global_assignment -name FAMILY Agilex
set_global_assignment -name IP_SEARCH_PATHS "intel_custom_ip/**/*;custom_ip/**/*"

# Fitter Assignments
# ==================
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name DEVICE AGFB027R24C2E2VR2
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_125MHZ
set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
#set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name USE_INIT_DONE SDM_IO0
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION OFF
set_global_assignment -name ENABLE_ED_CRC_CHECK ON
set_global_assignment -name MINIMUM_SEU_INTERVAL 10000
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"

# Assembler Assignments
# =====================
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE OTHER
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 6D
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-10"
set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD 0
set_global_assignment -name HPS_INITIALIZATION "HPS FIRST"

# Signal Tap Assignments
# ======================
set_global_assignment -name ENABLE_SIGNALTAP OFF

# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_APPLY_THERMAL_MARGIN ADDITIONAL

# ------------------------------------------
# start ENTITY(f_tile_soft_reset_ctlr_ip_v1)

# Project-Wide Assignments
# ========================

# end ENTITY(f_tile_soft_reset_ctlr_ip_v1)
# ----------------------------------------

# -------------------------
# start ENTITY(ftile_ag_v0)

# Project-Wide Assignments
# ========================

set_location_assignment PIN_DD38 -to jesd_sysref
set_location_assignment PIN_AJ49 -to jesd_gt_ref_clk
set_instance_assignment -name IO_STANDARD 1.2V -to cpld_100mhz -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD 1.2V -to cpld_reset_n -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to jesd_device_clock -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to jesd_sysref -entity ghrd_agilex_top
set_location_assignment PIN_DD36 -to jesd_device_clock
set_location_assignment PIN_AK52 -to tx_p[0]
set_location_assignment PIN_AG55 -to rx_p[0]
set_location_assignment PIN_AV52 -to tx_p[1]
set_location_assignment PIN_AR55 -to rx_p[1]
set_location_assignment PIN_AP52 -to tx_p[2]
set_location_assignment PIN_AL55 -to rx_p[2]
set_location_assignment PIN_R49 -to tx_p[3]
set_location_assignment PIN_K52 -to rx_p[3]
set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_p[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_p[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_p[1] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_p[1] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_p[2] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_p[2] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_p[3] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_p[3] -entity ghrd_agilex_top

set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to rx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to rx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=46" -to tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=0" -to tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=8" -to tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to eth_rx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to eth_rx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to eth_tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=5" -to eth_tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=0" -to eth_tx_p -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to eth_tx_p -entity ghrd_agilex_top

# -----------------------------
# start ENTITY(ghrd_agilex_top)

# Fitter Assignments
# ==================

# Design Partition Assignments
# ============================

# Logic Generation and Fitter Assignments
# =======================================

# end ENTITY(ghrd_agilex_top)
# ---------------------------

# Ordering Sensitive Assignments
# ==============================
set_global_assignment -name USE_SIGNALTAP_FILE prach_debug.stp
#set_global_assignment -name IP_FILE ../../designs/lib/qsys_comp/ip/ram_32i_32o_122kd_dc.ip
set_location_assignment PIN_DF34 -to DSP_CLK_491M
set_location_assignment PIN_T40 -to MASTER_TOD_PPS_IN
set_global_assignment -name SEED 1
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT timing_report.tcl
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 200
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2* -entity ghrd_agilex_top -disable
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2* -entity ghrd_agilex_top -disable
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay* -entity ghrd_agilex_top -disable

set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_cma0* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_cma1* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_wi0_r0_delayr*_mem_dmem* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_wi0_r0_delayr*_q* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_wi0_r0_delayr*_delay_* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_cma0* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_cma1* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_wi0_r0_delayr*_mem_dmem* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_wi0_r0_delayr*_q* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_im|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_im|u0_m0_wo0_wi0_r0_delayr*_delay_* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_cma0* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_cma1* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_wi0_r0_delayr*_mem_dmem* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_wi0_r0_delayr*_q* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l1_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_wi0_r0_delayr*_delay_* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_cma0* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_cma1* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_wi0_r0_delayr*_mem_dmem* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_wi0_r0_delayr*_q* -entity ghrd_agilex_top -disable
set_instance_assignment -name DUPLICATE_ATOM 100 -from soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theDDC_l2_vunroll_cunroll_x|theHB7_vunroll_cunroll_x|thescale_HB7_re|redist3_xIn_v_2_delay_0[0] -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|thechan_filter_re|u0_m0_wo0_wi0_r0_delayr*_delay_* -entity ghrd_agilex_top -disable
set_instance_assignment -name MAX_FANOUT 100 -to *theDUT_vunroll_cunroll_x|therouting_reg_hb72chan_l2_cunroll_x|redist0_ChannelIn_cunroll_x_in_2_dv_tpl_3_q* -entity ghrd_agilex_top -disable
set_instance_assignment -name MAX_FANOUT 100 -to *theDUT_vunroll_cunroll_x|therouting_reg_hb72chan_l1_cunroll_x|redist0_ChannelIn_cunroll_x_in_2_dv_tpl_3_q* -entity ghrd_agilex_top -disable
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|u_ifft_reg_map|ifft_shift_l1_1d[*] -entity ghrd_agilex_top -disable
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|u_ifft_reg_map|ifft_shift_l1_1d[*] -entity ghrd_agilex_top -disable
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_prach_top|u_prach_ant_mux|avst_sink_valid_1d_dup1* -entity ghrd_agilex_top -disable
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_prach_top|u_prach_ant_mux|avst_sink_valid_1d_dup1* -entity ghrd_agilex_top -disable
set_global_assignment -name VERILOG_FILE ../../designs/lib/qsys_comp/jesd204c_srcs/wn_JESD204C_200mhz_bw.v
set_global_assignment -name VERILOG_FILE ../../designs/lib/qsys_comp/jesd204c_srcs/wn_JESD204C_100mhz_bw.v
set_global_assignment -name SYSTEMVERILOG_FILE ../../designs/lib/qsys_comp/jesd204c_srcs/JESD204C_top.sv
set_global_assignment -name VERILOG_FILE ghrd_agilex_top.v
set_global_assignment -name SYSTEMVERILOG_FILE custom_ip/timing_adapter/timing_adapter.sv
set_global_assignment -name SYSTEMVERILOG_FILE custom_ip/timing_adapter/timing_adapter_fifo.sv
set_global_assignment -name IP_FILE ip/qsys_top/qsys_top_sc_fifo_0.ip
set_global_assignment -name IP_FILE gpio_ftile_outclk.ip
set_global_assignment -name VHDL_FILE measure_refclk.vhd
set_global_assignment -name VERILOG_FILE custom_ip/debounce/debounce.v
set_global_assignment -name VERILOG_FILE custom_ip/edge_detect/altera_edge_detector.v
set_global_assignment -name SDC_FILE ghrd_timing.sdc
set_global_assignment -name SDC_FILE ftile_25gbe.sdc
set_global_assignment -name QSYS_FILE qsys_top.qsys
set_global_assignment -name QSYS_FILE ftile_subsys.qsys
set_global_assignment -name QSYS_FILE master_tod_subsys.qsys
set_global_assignment -name QSYS_FILE rx_tod_subsys.qsys
set_global_assignment -name QSYS_FILE tx_tod_subsys.qsys
set_global_assignment -name QSYS_FILE dma_subsys.qsys
set_global_assignment -name QSYS_FILE subsys_ftile_25gbe_rx_dma.qsys
set_global_assignment -name QSYS_FILE subsys_ftile_25gbe_tx_dma.qsys
set_global_assignment -name QSYS_FILE hps_subsys.qsys
set_global_assignment -name IP_FILE ip/qsys_top/clk_100.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_in.ip
set_global_assignment -name IP_FILE ip/qsys_top/ninitdone_rst.ip
set_global_assignment -name IP_FILE ip/qsys_top/sysid.ip
set_global_assignment -name IP_FILE ip/qsys_top/tod_clk_156.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_156_tod.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_201.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_390_ftile_rec_div.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_390_ftile_tx_div.ip
set_global_assignment -name IP_FILE ip/qsys_top/ftile_390_clkout_1588.ip
set_global_assignment -name IP_FILE ip/qsys_top/ftile_ref_sys_clk.ip
set_global_assignment -name IP_FILE ip/qsys_top/ftile_debug_status_pio.ip
set_global_assignment -name IP_FILE ip/qsys_top/avmm_csr.ip
set_global_assignment -name IP_FILE ip/qsys_top/user_rst_clkgate_0.ip
set_global_assignment -name IP_FILE ip/qsys_top/axi_bridge_for_acp_0.ip
set_global_assignment -name IP_FILE ip/qsys_top/dma_clk_out.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ftile_clk.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ftile_hip.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ftile_ptp_sampling_pll.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ftile_clk_tx_div.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ftile_clk_rec_div.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/scan_tod_clk.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/master_tod_rst.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/pll_tod_rst.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/csr_tod_clk.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/master_tod.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/tod_pll_interface_adapter_0.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/sync_sampling_pll.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/period_clock_source.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/master_sampling_iopll.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/master_phase_iopll.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/master_tod_load_off_96b.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/master_tod_load_off_64b.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/tod_sync_interface_adapter_0.ip
set_global_assignment -name IP_FILE ip/rx_tod_subsys/rx_tod_synchronizer.ip
set_global_assignment -name IP_FILE ip/rx_tod_subsys/rx_tod_slave.ip
set_global_assignment -name IP_FILE ip/rx_tod_subsys/rx_tod_slave_load_off_64b.ip
set_global_assignment -name IP_FILE ip/tx_tod_subsys/tx_tod_synchronizer.ip
set_global_assignment -name IP_FILE ip/tx_tod_subsys/tx_tod_slave.ip
set_global_assignment -name IP_FILE ip/tx_tod_subsys/tx_tod_slave_load_off_64b.ip
set_global_assignment -name IP_FILE ip/dma_subsys/iopll_clk_avst_div2.ip
set_global_assignment -name IP_FILE ip/dma_subsys/ftile_st_adapter.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_1588_dmaclkout_reset.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_1588_dmaclkout.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_clock.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_ftile_clock.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_tx_dc_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_reset.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_timestamp_insert.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_fingerprint_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_fingerprint_compare.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_prefetcher.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_tx_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_csr.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_timestamp_req.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_ts_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_read_master.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_dispatcher.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_tx_dma/tx_dma_timestamp_adapter.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_prefetcher.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_csr.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_ftile_clock.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_dispatcher.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_write_master.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_timestamp_adapter.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_pkt_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_ts_insert.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_pause_ctrl.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_ts_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_clock.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_pkt_dc_fifo.ip
set_global_assignment -name IP_FILE ip/dma_subsys/subsys_ftile_25gbe_rx_dma/rx_dma_reset.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_lw_clkin.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_lw_rstin.ip
set_global_assignment -name IP_FILE ip/hps_subsys/emif_fm_hps.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_lw_bridge.ip
set_global_assignment -name IP_FILE ip/hps_subsys/f2h_clkin.ip
set_global_assignment -name IP_FILE ip/hps_subsys/f2h_rstin.ip
set_global_assignment -name IP_FILE ip/hps_subsys/f2h_bridge.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_clkin.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_rstin.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_bridge.ip
set_global_assignment -name IP_FILE ip/hps_subsys/fbr_ddr4A_clk.ip
set_global_assignment -name IP_FILE ip/hps_subsys/fbr_ddr4B_clk.ip
set_global_assignment -name IP_FILE ip/hps_subsys/fbr_ddr4A_rst.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_fbr_ddr4A.ip
set_global_assignment -name IP_FILE ip/hps_subsys/fbr_ddr4B_rst.ip
set_global_assignment -name IP_FILE ip/hps_subsys/h2f_fbr_ddr4B.ip
set_global_assignment -name IP_FILE ip/hps_subsys/hps.ip
set_global_assignment -name IP_FILE ip/hps_subsys/emif_cal.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_402.ip
set_global_assignment -name IP_FILE ip/qsys_top/ocm.ip
set_global_assignment -name IP_FILE ip/qsys_top/f2h_axi_rst.ip
set_global_assignment -name IP_FILE ip/qsys_top/h2f_axi_rst.ip
set_global_assignment -name IP_FILE ip/qsys_top/h2f_lw_axi_rst.ip
set_global_assignment -name IP_FILE ip/qsys_top/fpga_m2ocm_pb.ip
set_global_assignment -name IP_FILE ip/qsys_top/ext_hps_m_master.ip
set_global_assignment -name IP_FILE ip/qsys_top/ftile_hip_i_tx_rst_n_reset.ip
set_global_assignment -name QSYS_FILE subsys_periph.qsys
set_global_assignment -name IP_FILE ip/subsys_periph/periph_clk.ip
set_global_assignment -name IP_FILE ip/subsys_periph/periph_rst_in.ip
set_global_assignment -name IP_FILE ip/subsys_periph/button_pio.ip
set_global_assignment -name IP_FILE ip/subsys_periph/dipsw_pio.ip
set_global_assignment -name IP_FILE ip/subsys_periph/led_pio.ip
set_global_assignment -name IP_FILE ip/subsys_periph/ILC.ip
set_global_assignment -name IP_FILE ip/subsys_periph/pb_cpu_0.ip
set_global_assignment -name QSYS_FILE subsys_jtg_mst.qsys
set_global_assignment -name IP_FILE ip/subsys_jtg_mst/jtag_clk.ip
set_global_assignment -name IP_FILE ip/subsys_jtg_mst/jtag_rst_in.ip
set_global_assignment -name IP_FILE ip/subsys_jtg_mst/hps_m.ip
set_global_assignment -name IP_FILE ip/subsys_jtg_mst/fpga_m.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/rst_ptp_adapter_clk_402.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ptp_adpt_rst_clk_402.ip
set_global_assignment -name IP_FILE ip/ftile_subsys/ptp_tile_adpt.ip
set_global_assignment -name IP_FILE ip/qsys_top/ptp_adpt_o_clk_pll_402.ip
set_global_assignment -name IP_FILE ip/tx_tod_subsys/tx_stod_valid_gen.ip
set_global_assignment -name IP_FILE ip/rx_tod_subsys/rx_stod_valid_gen.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/mtod_load_off.ip
set_global_assignment -name IP_FILE ip/master_tod_subsys/mtod_valid_gen.ip
set_global_assignment -name IP_FILE iopll_390p625.ip
set_global_assignment -name IP_FILE iopll_491p52.ip
set_global_assignment -name IP_FILE ip/qsys_top/clk_390.ip
set_global_assignment -name IP_FILE ip/qsys_top/clk_491.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_390.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_clk_491.ip
set_global_assignment -name IP_FILE ip/qsys_top/rst_ftile_clk_402.ip
set_global_assignment -name IP_FILE ../../generated/eth/fdv_buffer/ip/ram_48i_48o_36d_dc.ip
set_global_assignment -name IP_FILE ../../generated/eth/fdv_buffer/ip/ram_128i_32o_3276d_dc.ip
set_global_assignment -name IP_FILE ../../generated/ORAN/oran_hwtcl_top_ex_design/synthesis/ip_components/oran_hwtcl_top.ip
set_global_assignment -name IP_FILE ../../generated/eCPRI/ecpri_hwtcl_top_ex_design/synthesis/ip_components/ecpri_hwtcl_top.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_8i_8o_64d_dc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_64i_64o_4096kd.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_32i_32o_1024d_sc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_32i_32o_1024d_dc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_32i_128o_8d_dc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_32i_128o_1024d_dc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_128i_128o_4096d_sc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_128i_128o_2048d_sc.ip
set_global_assignment -name IP_FILE ../../generated/fft_ifft/ip/ff_128i_128o_1024d_sc.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys_comp/ip/ff_32i_32o_32kd_sc.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys_comp/ip/ff_32i_64o_16d_dc.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys_comp/ip/ff_96i_96o_4096kd.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_mm_pb_h2f_bridge.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_wrapper_top.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_rst_csr.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_mm_h2flw_bridge.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_rst_dsp.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_csr.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_dsp.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_eth25g_tx.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_ecpri_tx.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_eth25g_rx.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_ecpri_rx.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_mm_h2f_bridge.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_mm_pb_h2f_lw_bridge.ip
set_global_assignment -name IP_FILE ../../designs/lib/qsys/ip/wrapper/wrapper_clk_prach.ip
set_global_assignment -name IP_FILE ip/qsys_top/qsys_top_tod_timestamp_96b_0.ip
set_global_assignment -name QSYS_FILE ../../designs/lib/qsys/wrapper.qsys
set_global_assignment -name SDC_FILE wrapper.sdc
set_global_assignment -name SDC_FILE ../../generated/ORAN/oran_hwtcl_top_ex_design/synthesis/quartus/oran_ed_agilex.sdc
set_global_assignment -name SDC_FILE ../../generated/eCPRI/ecpri_hwtcl_top_ex_design/synthesis/quartus/ecpri_ed_agilex.sdc
set_global_assignment -name SDC_FILE ../../designs/dspba/DDC/rtl/ddc_2c4ant/ddc_2c4ant_DUT.sdc
set_global_assignment -name IP_FILE ip/qsys_top/cdc_pipeline_0.ip
set_global_assignment -name TCL_SCRIPT_FILE timing_report.tcl
set_global_assignment -name IP_FILE ip/master_tod_subsys/eth_1588_pps.ip
set_global_assignment -name IP_FILE jesd204c_100mhz_bw.ip
set_global_assignment -name IP_FILE device_clock_pll_100mhz.ip
set_global_assignment -name IP_FILE jesd204c_ftile_clocking_100mhz.ip
set_global_assignment -name FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD ON
set_instance_assignment -name IO_STANDARD 1.2V -to FBR_CLK_100M -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD 1.2V -to MASTER_TOD_PPS -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "CURRENT MODE LOGIC (CML)" -to FTILE_REFCLK -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FTILE_TX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to TOD_REFCLK -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to FTILE_OUTCLK -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to FTILE_RX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to FTILE_RX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to FTILE_RX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to FTILE_TX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to FTILE_TX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to FTILE_TX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to FTILE_TX_SERIAL[0] -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to DSP_CLK_491M -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|tod_0|tod_timestamp_96b_ts_buf|tod_timestamp_96b_ts_buf|*seconds* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|tod_0|tod_timestamp_96b_ts_buf|tod_timestamp_96b_ts_buf|*seconds* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|tod_0|tod_timestamp_96b_ts_buf|tod_timestamp_96b_ts_buf|rfp_sync_pul* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_xran_timestamp|frame_status_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|xran_demapper_cplane_dout_ul_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|xran_demapper_cplane_vout_ul_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|xran_demapper_cplane_vout_ul_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_frame_sync|auxN_tx_rfp_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_gain_l1_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_gain_l1_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|fft_gain_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|fft_gain_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|muxsel_l1_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|muxsel_l1_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|fft_shift_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_mux_const_l1_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|hcs_bypass_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|hcs_bypass_1d* -entity ghrd_agilex_top
set_instance_assignment -name IO_STANDARD "1.2 V" -to MASTER_TOD_PPS_IN -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 1000 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|rst_dsp_n_2d_dup1* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 400 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_source_valid* -entity ghrd_agilex_top
set_instance_assignment -name DUPLICATE_REGISTER 20 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|u_ifft_blocktostream_DL_OFDM|reset_fanout_mitigation_signal_out[*] -entity ghrd_agilex_top
set_instance_assignment -name DUPLICATE_REGISTER 20 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|u_streamtoblock_fft_DUT|reset_fanout_mitigation_signal_out[*] -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 75 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|duc_inst|theChanFilt_DUC_vunroll_cunroll_x|thePoly_phase_Interp_vunroll_cunroll_x|thescale_HB8_re|redist24_xIn_v_2_delay* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 75 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|duc_inst|theChanFilt_DUC_vunroll_cunroll_x|thePoly_phase_Interp_vunroll_cunroll_x|thescale_HB8_re|redist24_xIn_v_2* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|tod_0|tod_timestamp_96b_ts_buf|tod_timestamp_96b_ts_buf|rfp_sync_pul* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_xran_timestamp|frame_status_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|xran_demapper_cplane_dout_ul_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_frame_sync|auxN_tx_rfp_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|u_fft_if|fft_shift_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_mux_const_l1_1d* -entity ghrd_agilex_top
set_instance_assignment -name DUPLICATE_REGISTER 20 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|duc_inst|reset_fanout_mitigation_signal_out[*] -entity ghrd_agilex_top
set_instance_assignment -name DUPLICATE_REGISTER 50 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|reset_fanout_mitigation_signal_out* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 400 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_source_data* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|therouting_reg_chan_re|redist0_ChannelIn_in_2_dv_tpl_3_q* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_Filter_l1_cunroll_x|theChan_Filter_cunroll_x|therouting_reg_chan_im|redist0_ChannelIn_in_2_dv_tpl_3_q* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|therouting_reg_chan_re|redist0_ChannelIn_in_2_dv_tpl_3_q* -entity ghrd_agilex_top
set_instance_assignment -name MAX_FANOUT 100 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_ul_top|ddc_inst|theDUT_vunroll_cunroll_x|theChan_FIlter_l2_cunroll_x|theChan_Filter_cunroll_x|therouting_reg_chan_im|redist0_ChannelIn_in_2_dv_tpl_3_q* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_dl_fdv_buffer|ram_rden_dup_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_dl_fdv_buffer|ram_rden_dup_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_dl_fdv_buffer|ram_rdaddress_dup_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_dl_fdv_buffer|ram_rdaddress_dup_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_radio_config|blank_prb_flag_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_radio_config|blank_prb_flag_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_prach_top|u_prach_ant_mux|timing_reference_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_prach_top|u_prach_ant_mux|timing_reference_1d* -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_shift_l1_1d[*] -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|ifft_shift_l1_1d[*] -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|Digital_pow_scale_l1_1d[*] -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to *|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_dl_top|u_ifft_if|Digital_pow_scale_l1_1d[*] -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_prach_top|prach_pat_en_1d -entity ghrd_agilex_top
set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to soc_inst|wrapper_0|wrapper_wrapper_top|wrapper_wrapper_top|u_prach_top|prach_pat_en_1d -entity ghrd_agilex_top
set_instance_assignment -name PARTITION_COLOUR 4284809125 -to JESD204C_top -entity ghrd_agilex_top
set_instance_assignment -name PARTITION_COLOUR 4292607854 -to auto_fab_0 -entity ghrd_agilex_top
set_location_assignment PIN_DC39 -to "jesd_sysref(n)"
set_instance_assignment -name PARTITION_COLOUR 4294929372 -to ghrd_agilex_top -entity ghrd_agilex_top

Harshx · ‎05-13-2024

Hi,

Can you please share only IP files (.ip) for JESD and Ethernet?

Regards,

Harsh

Facing some placement issue in F-tile of agilix board, while trying to compile Ethernet and JESD204C

Hardware malfunction|Board Design File