SoC Cyclone V : FPGA full configuration from HPS FPGA Manager, MSEL issue ?

[WabG]

Dear support,

We are using a SoC cyclone V and want to configure the FPGA portion from HPS through the FPGA manager.

We have followed the procedure described in HPS Technical Reference Manual (cv_5v4 - 2022.11.14) but it didn't succeed while all the registers status correspond to the procedure.

The main difference is the MSEL configuration: in our system MSEL[4:0] = 0x13 and this is not an appropriate configuration following the HPS manual but, in the same time, the register FPGAManager.Ctrl specify the bit EN to take the control over the configuration:

My question is : is it possible to configure the FPGA with a wrong MSEL setting ?

Regards,

WabG

[aikeu]

Hi WabG,

To configure the FPGA, you will need to perform 'bridge enable' cmd in Uboot.

Try to run bridge enable then only configure/load the FPGA bitstream.

Thanks.

Regards,

Aik Eu

[WabG]

Aik Eu,

Even with the bridge enable command, the FPGA isn't configured under U-Boot.

But, with a good MSEL setting, the FPGA load is successful.

Do you confirm, it is possible to use the FPGA manager to load the FPGA portion even with a wrong MSEL setting ?

How the bit enable of control register of FPGA Manager should be interpreted ?

En bit = 1 : "FPGA Manager drives configuration inputs to the CB. Used when HPS configures the FPGA."

My interpretation was "FPGA manager" bypasses the MSEL setting when the bit is set to 1.

Regards,

WabG

[aikeu]

Hi WabG,

I not able to confirm about the particular MSEL thing. By default, simply booting up from qspi or sd card, we dont purposely do any changes to the MSEL settings, the FPGA configuration still can be loaded with quartus programmer or using FPGA load cmd in Uboot. I suggest working with the default working settings then only try to make the changes in order to see if that affects the FPGA configuration load operation.

Thanks.

Regards,

Aik Eu

[FvM]

Hi,
FPGA Manager specification, Table 4.1 is pretty clear about this point, I believe. FPGA configuration from HPS is only supported for FPPx32 and FPPx16 MSEL setting.

[WabG]

Hello,

This isn't so clear on the control register description of the FPGAManager : "Controls whether the FPGA configuration pins or HPS FPGA Manager drive configuration inputs to the CB."

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410067797617.html

Regards,

WabG

[WabG]

Aik Eu,

I have tried to load the FPGA from UBoot with the good and wrong MSEL setting: as described in the FPGA Manager only the good MSEL allows the configuration.

The control register description of the FPGAManager  "Controls whether the FPGA configuration pins or HPS FPGA Manager drive configuration inputs to the CB." must not to be interpreted as the MSEL setting are bypassed with this register.

Regards,

WabG

[aikeu]

Hi WabG,

Sorry for my late respond. You did mentioned about good and wrong MSEL select. What are the settings that you use while successfully load the FPGA configuration and what settings does not work?

Would like to know also if the settings that you have mentioned only applies to your custom board?

Thanks.

Regards,

Aik Eu

[aikeu]

Hi WabG,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks.

Regards,

Aik Eu