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KLohr
Novice
437 Views

For the Max10 fpga peripheral clock it says: "Table 31. Peripheral Clock Interface Signals ... Note: To avoid functional failure, the required minimum peripheral clock frequency is 25 MHz"

I have a design that feeds both clocks of the ADC with a 2Mhz clock (from the PLL) and it seems to work fine for the Temperature Sense Diode. Our System clock for the FPGA is only 4Mhz. Does that mean we can't use the ADC for other functions?

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GuaBin_N_Intel
Employee
33 Views

User must follow the note to run at minimum peripheral clock 25MHz for ADC core clock. Once violated, it will cause unexpected result when running it on hardware/board.
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