HPS BareMetal LED toggle Example for Altera Cyclone V Developement Ki

[Chandrashekhar_K]

Kindly share working example to toggle LED/GPIO of HPS
Kit : Cyclone V SoC Development Board

Platform : Bare Metal 

[mabdrahi]

Hi,

I will try to find, test on my side and give my reference project to you

[mabdrahi]

Hi,

I found the useful reference about the project

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_cv_soc_dev_kit.pdf

I will try this at my end

[mabdrahi]

Hi,

Can you try this example?

https://www.rocketboards.org/foswiki/pub/Projects/LEDBlink/led_blink.tgz

Is it suit with your project?

[Chandrashekhar_K]

Hi Mabdrahi,

Thank you3 for sharing the document and the  LED example.
I think the example is for linux environment. 
It would be of great help if the code for bare metal is available.

Thank You

[mabdrahi]

Hi,

I found a useful link for you to try.

https://www.rocketboards.org/foswiki/Documentation/HWLib

[mabdrahi]

Hi,

Any update at your end?

[Chandrashekhar_K]

I could get a sample example from the community, struggled a bit to get it complied.  

Now the LED example is working.

Thank you.

[mabdrahi]

Hi Chandra,

I hope you doing well,

Any stuck or progress status on your end?

[mabdrahi]

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[ALTERA-INSUPPORT22]

Assistance Needed: Trouble Running Bare-Metal Code on Cyclone 5 HPS
I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal .

When I run in jtag mode it works, for jtag i first debug using core 0 where i take core 1 out of reset it, than debug core 1 usign jtag it work

BUT, When i want to run both core usign qspi it only run core 0 not core 1

Here is the step i followed

Firsly, loading preloader
quartus_hps -c 1 -o P preloader-mkpimage.bin

I make an image from bin file of core 0 and place it to qspi

mkimage -A arm -O u-boot -T standalone -C none -a 0x00060000 -e 0 -n "baremetal image" -d core0.bin core0.img

quartus_hps -c 1 -o P -a 0x00060000 core0.img

I make an image from bin file of core 1 and place it to qspi
mkimage -A arm -O u-boot -T standalone -C none -a 0x00100000 -e 0 -n "baremetal image" -d core1.bin core1.img
quartus_hps -c 1 -o P -a 0x00100000 core1.bin

When i restart board only that code work which is in core 0, core 1 code not executing

I am setting cpu1startaddress 100000 apart from that in the code of core 0 also i am using alt_qspi function to to place bin file data in ddr, 

I want to run in smp mode so I also set required aux_control_register smp and fw bit as stated in tech ref manual  

alt_qspi_read((uint32_t *)BL_START/*ddr3 address*/, 0x100000/*qspi address*/, 0x40000);

In linker/scat file core 0 entry point is 0x60000 and

linker/scat file core 1 entry point is 0x100000