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HPS access the Avalon Memory-Mapped whether in pending status

Jacob999
Beginner
146 Views

I use Avalon Memory-Mapped (Avalon-MM) interfaces to implement read and
write interfaces for master and slave components. HPS side is master and FPGA side is slave.

I find that HPS software code could not be pending when HPS launch one write/read transmission in waitrequest mode(the Avalon slave asserts waitrequest signal).

In the document description, " A slave asserts waitrequest when unable to respond to a
read or write request. Forces the master to wait until the interconnect is ready to proceed with the transfer. At the start of all transfers, a master initiates the transfer and waits until waitrequest is deasserted."  My question is how about the HPS write/read MM software code, whether also be pending like the Avalon master, how about that scheme need to be configured if we want to pend software code runs on ARM? 

  

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3 Replies
JingyangTeh
Employee
123 Views

Hi Jacob

 

Are you referring to a flow control within the HPS?

 

For more information on the Flow Control between the Master and Slave you could refer to the document:

https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/typical-read-and-write-transfe...

 

 

Regards

Jingyang,Teh

JingyangTeh
Employee
103 Views

Hi Jacob

 

Any update on this case?

 

Regards,

Jingyang, Teh

JingyangTeh
Employee
89 Views

 Hi Jacob

 

We did not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Regards

Jingyang, Teh

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