FPGA, SoC, And CPLD Boards And Kits
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Hi! I have Cyclone10 GX devkit. Is it possible to make a soft start on the output pins? If yes, then how to configure it Quartus 18.0 SE?

Длаза
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AR_A_Intel
Employee
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Hello,

Good day

 

Welcome to INTEL forum. Sorry as I read through the description, I am not sure on what is the specific enquiry.

Could you elaborate more what do you means by “Is it possible to make a soft start on the output pins” ? Are you trying to learn how to do Quartus design or learn how to assign FPGA pins in the dev kit board?

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Длаза
Novice
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I am learn how to assign FPGA pins. Soft start is when the output voltage rises slowly.

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ShafiqY_Intel
Employee
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Hi Длаза ,

 

You can use Assignment Editor or Pin Planner to assign FPGA pin in Quartus.

 

Go to Quartus>Assignments>Assignment Editor/Pin Planner

 

In Assignment Editor or Pin Planner, you can assign pin location, I/O standard, Current strength and etc.

 

Below is example how Pin Planner looks like:

Screenshot (224).png

 

Thanks

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Длаза
Novice
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If I use "slew rate=0" in assignment editor, then how slowly will the output voltage rise?

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ShafiqY_Intel
Employee
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Hi Длаза ,

 

We do not have the value as per your request.

We apologize for inconvenience.

 

Thanks

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