I am working with an Stratix 10 GX development kit, and I have a problem with the example design loopback_Host Pipe. When the host communicate with the OpenCL command clSetKernelArg(kernel, 0, sizeof(cl_mem), (void *)&write_pipe), the following assert is shown:
host: acl_hal_mmd.c:2486: acl_hal_mmd_hostchannel_create: Assertion `device_info[physical_device_id].mmd_dispatch->aocl_mmd_hostchannel_create' failed.
This problem just happens with host pipes.
How can I solve this?
Thanks in advance.
The source code that I used is the example in:
The aocl version is:
aocl 22.214.171.124 (Intel(R) FPGA SDK for OpenCL(TM), Version 18.1.0 Build 222 Pro Edition
That means, the 18.1 do not have support for the host-pipe example such as the software and hardware requirements suggest?.