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How can I simulate dedicated high speed clock input pins in HyperLynx by FPGA's IBIS model?

LFang7
Beginner
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Hi,

I download  EP4SE530's IBIS model, but I can not find the dedicated high speed clock input pins in the model. The pin name is CLK[1,3,8,10]. So how can I simulate dedicated high speed clock input pins in HyperLynx by FPGA's IBIS model?IBIS model list.png

Yours,

Longyu

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YuanLi_S_Intel
Employee
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Hi Fang Longyu, There is no dedicated IBIS model for these pin. Since the I/O Standard in Intel PSG FPGA is programmable, you may use the I/O standard that you choose for that input clock pin as the IBIS model. Example: if you use 2.5V I/O standard, you can use 2.5Vcmos IBIS model. Regards, YL

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YuanLi_S_Intel
Employee
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Hi Fang Longyu, There is no dedicated IBIS model for these pin. Since the I/O Standard in Intel PSG FPGA is programmable, you may use the I/O standard that you choose for that input clock pin as the IBIS model. Example: if you use 2.5V I/O standard, you can use 2.5Vcmos IBIS model. Regards, YL
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