How can we generate a design for FPGA2 on Stratix V Advanced Systems Development Kit without any timing violations within the DDR3 SDRAM Controller IP Component?

[CEnde]

We're using the Stratix V Advanced Systems Development Kit for video processing and got a fundamental timing problem with the second FPGA on this board. Both FPGAs run almost exactly the same design (there are only minor differences caused by different connectors for the SDI transceivers). For FPGA1 the fitter is able to produce a design without any timing violations. For FPGA2 we always get timing violations within the DDR3 x32 IP Component (DDR3 SDRAM Controller with UniPHY v16.0), even if we drastically reduce the amount of processed channels.

While searching for the cause of this error, I made a very suspicious observation. I started to compare our design with a minimal example design, provided by Altera for the exact same development board. When I compiled the example design without changing anything I also got timing violations reported within this IP Component. I'm asking myself, how it comes that even Altera can't provide a good working example on how to properly use the memory interface. Maybe, the IP Component is generated using a wrong parametrization? I was surprised, that both FPGA IP Components are generated, using the same board skew parameters, although the board layout makes me assume different trace lengths.

Thank you very much for your help! All suggestions are appreciated!

I'm working with Quartus Prime Version 16.0.1 on Windows 7.

We use the following development board:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-stratix-v-advanced.html

The example designs are also given on this page and are contained in the archive, which can be downloaded by clicking on Kit Installation in the documentation section.

[BoonT_Intel]

Hi CEnde,

Stratix V EMIF using soft memory controller and the timing is sensitive to pin location.

The dev kit is develop prior to timing model finalized. Thus, the pin location of the dev kit cannot change after timing model is finalize and we aware that timing is not fully clean with that pin location.

However, since dev kit is work in typical condition (typical voltage and temperature). Thus, it is still work reliable even timing is not clean. Therefore, it is still acceptable even timing is not clean since the design is work correctly on the board.

However, if customer develop their customer board, we advise to get a pin location that meet timing, then only tape-out their board design.

Sincerely hope this explanation is making sense to you.

Thanks

[CEnde]

Thank you for your reply! Your explanation sounds plausible to me, although I was hoping for an error case with a simpler solution.

Since there is a clear difference in performance between both Stratix V FPGAs, we assume that these problems have a crucial impact on our use case.