How high frequency can DE2 board reach?

[Altera_Forum]

Hi there, 

see subject, I want to know how fast DE2 board can run, does anyone happen to know?  I mean the DE2 education board, the cpu is EP2C35F672C6 .

[Altera_Forum]

Dear irun2, 

   --- Quote Start ---  I want to know how fast DE2 board can run, does anyone happen to know? I mean the DE2 education board, the cpu is EP2C35F672C6 .  --- Quote End ---     EP2C35 is not a cpu but an FPGA. You could of course design cpu's inside.   The maximum speed of circuits in FPGA's depends on their design, the depth of the logic and the interconnection. You can make estimates of the timing performance by means of the Quartus-II tool called "Classic Timing Analyzer" which is simple to use and gets you a reasonable estimate. If you want more accurate timing analysis you can use better constraints and get more accurate estimates by the TimeQuest tool.   When designing circuits you can get higher speeds by keeping the combinatorial logic depth low. This can be done by making pipelined designs.   So it depends.   For small circuits you should be able to get speeds over 200MHz. For more complicated circuits it could be that you only get 100MHz or even lower.   It depends on the cleverness and complexity of your design.   hope this helps...

[Altera_Forum]

--- Quote Start ---  Dear irun2,       EP2C35 is not a cpu but an FPGA. You could of course design cpu's inside.   The maximum speed of circuits in FPGA's depends on their design, the depth of the logic and the interconnection. You can make estimates of the timing performance by means of the Quartus-II tool called "Classic Timing Analyzer" which is simple to use and gets you a reasonable estimate. If you want more accurate timing analysis you can use better constraints and get more accurate estimates by the TimeQuest tool.   When designing circuits you can get higher speeds by keeping the combinatorial logic depth low. This can be done by making pipelined designs.   So it depends.   For small circuits you should be able to get speeds over 200MHz. For more complicated circuits it could be that you only get 100MHz or even lower.   It depends on the cleverness and complexity of your design.   hope this helps...  --- Quote End ---     Thanks for your detailed explanation! But i still have one concern, say when dealing with a SPI interface design in DE2, from the timing analyse report we get the speed the device EP2Cxx can run, but how do we know if it's safe and stable when it's running on the board? I guess somewhat it's related to the board's design...   Pleas kindly correct me if I am wrong! ;)

[Altera_Forum]

The interconnect delay on the DE2 board is maximum a few nsec. 

 The SPI device on the DE2 board requires a minimum clock period of 80 nsec. So board interconnect delay is only a few percent of this.   You have to design your circuit in such a way that it generates signals according to the circuit you want to interface with. Given that you use a system clock frequency of 50MHz or higher on your DE2, making an interface to a SPI device should not be constraint by delays in your FPGA or on your board. The maximum speed of your FPGA and board should be more than enough for SPI.