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How to access DDR3 memory on a DE10 Nano board (Cyclone V)?



I would like to access the HPS DDR3 RAM from the FPGA. The goal would be to have a RAM module on the FPGA side that would allow reading or writing to a certain address every time it is updated. But I want only one value to be stored on the FPGA side, I don't want to have a big on chip memory block that just copies a block of the same size on the DDR3 side. The idea is really to have access to a large amount of memory on the DDR3 side and to access it only by the address, reading and writing one value at a time.

The problem is that even after doing quite a bit of googling and reading the terasic manuals and demonstrations, I still can't build my system. I'm having trouble seeing the steps to follow and how to get everything right. I understand that I'm supposed to use the FPGA-to-HPS bridge (I don't want to use the ram bridge as it isn't cache coherent) and do memory mapping, but after that I can't get it in place. Is there someone who can guide me?


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