I have an old FPGA board running on Cyclone III which has Verilog files but doesn't have any bdf, so it was difficult tracking the connections. Now I want to rewrite the programs for the new Cyclone V (Terasic DE0 Nano-SoC) board that I purchased. However, the Cyclone III code uses ftdi-usb communication and the new board uses Virtual JTAG communication. So the format of the code are mostly different. Also, the cyclone III code uses .qip files along with Verilog files. How should I go about rewriting this code and what factors must I consider while doing this? Any advice would be greatly appreciated.
Hi @AAjit2 ,
We can use our old design with little modification by considering below points.
Generate correct IP file , add it to project , integrate it top top-level file & compile the designa nd check
QIP file is Quartus IP file which is generated which generating IP from mega-wizard or IP catalog.
If possible share the project.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.