Please someone guide. It seems the ref clk and tx rx serial data are single ended. And in fitting stage it shows error.
You can refer to Stratix 10 datasheet to find out the supported differential IO standard for the transcevier channel (depends on Ltile, Htile or Etile)
After that, you can use quartus assignment editor to set the desired differential IO standard for your transceiver refclk and receiver channel pins.