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Please someone guide. It seems the ref clk and tx rx serial data are single ended. And in fitting stage it shows error.
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HI,
You can refer to Stratix 10 datasheet to find out the supported differential IO standard for the transcevier channel (depends on Ltile, Htile or Etile)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf
After that, you can use quartus assignment editor to set the desired differential IO standard for your transceiver refclk and receiver channel pins.
Thanks.
Regards,
dlim
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