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Honored Contributor I
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How to find FIFO ID in FPGA architecture

Hi, 

 

To write data to a FIFO on FPGA from host through PCIE in DMA mode, by using Terasic PCIE IP, I need to specify the 'memory FIFO ID', how can I find the corresponding ID of a certain FIFO on FPGA architecture? 

Similarly, if this time the data is written to a memory-mapped memory, how to find the MM-address of the memory? 

 

I understand in SOPC/Qsys a certain base address is allocated to each component in the system, then does that mean Terasic PCIE IP has to be used with SOPC/Qsys? (doesn't look so from their reference design), then how to find the ID and the MM-address? 

 

Thanks!
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