I want to test 10GE MAC IP on A10SOC Dev Kit SFP+ port.
According to ug-20016, for 10ge case, one clock 644.53125MHZ is needed to feed into A10 “dedicated transceiver”.
Unfortunately on A10SOC Dev brd, only U42 "Si5338A" can be reprogrammed to generate the wantted 644.53125MHZ, but U42 's output clock are connected to FPGA IO BANK CLK pin, not the Transceiver's REFCLK_GXBCLK_xx ???
So where to get a 644.53125MHZ, that can be used to test 10GE functionality on A10SOC Dev Board, ( I believed Intel had verified this 10ge in past yet) ?
Pls advises, Thanks
As I look into the UG-20016 | 2019.09.23, it seems like the hardware validation was done using Intel Arria 10 GX Transceiver Signal Integrity Development Kit but not the A10 SOC devkit. As I look into the A10 SOC devkit, seems like there is no specific refclk source of 644.53125MHz for the 10GE example design testing. Sorry for the inconvenience. You might want to use A10GX SI devkit for the validation as per the user guide.
Please let me know if there is any concern. Thank you.
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