EDIT: Apologies, I'm an idiot. I just realized that the reason for the clock delay is because I'm using a register to store the address of the memory in another module. That's why it's taking one extra cycle. Effectively, my design is doing:
So my problem is not really with the way the RAM is designed. It's with the fact that that I can only access memory location using the address register.
ORIGINAL QUESTION BELOW:
When using a Single clock single port synchronous RAM, it appears that the data that I store in memory won't be available to read at least until one clock cycle later.
What I want to be able to do is:
But when I use the code below, I end up having to do:
If I use an asynchronous single port RAM, it works as expected but I can't utilise the block ram on my FPGA.
My question is - Is this expected, or am I doing something wrong? If this is expected, is there any way to have the code be synthesized to BRAM while being able to access it immediately after?
The code I'm using is identical to the one on this page.
module ram_infer ( input [7:0] data, input [5:0] read_addr, write_addr, input we, clk, output reg [7:0] q ); // Declare the RAM variable reg [7:0] ram[63:0]; always @ (posedge clk) begin if (we) ram[write_addr] <= data; q <= ram[read_addr]; end endmodule