How to thermally simulate an FPGA accurately

[MTayl21]

Hi all,

I am looking to investigate in more detail how to accurately simulate an FPGA device for temperature in a CFD solver.

Currently, all the information I can gather from various sources suggests to use the Psi_JC value given in the Power Estimator spreadsheet and apply a uniform power load to the thermal model. This gives highly inaccurate results as I would be expecting the FPGA silicon to have non-linear loading characteristics depending on the use case.

Some of the Intel documents show a thermal gradient on the die itself. Has anyone done investigation into how this can be achieved with greater accuracy?

I hope some other people have done some invesitgative work into this also as I do not want to be over- or under- sizing my thermal solutions.

Many thanks in advance for your help

[EngWei_O_Intel]

Hi Taylor-Smith

Can you refer to the link below if it meets your usage requirement? The Early Power Estimator (EPE) and Intel Quartus® Prime software power analyzer give the ability to estimate power consumption from early design concept through design implementation:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/operation-and-testing/power/pow-powerplay.html

The accuracy will get improved once we have the design implementation using Power Analyzer.

Thanks.

Eng Wei

[MTayl21]

Hi there, No that doesn’t give the granularity sorry. The spreadsheet provides a total power and a JC resistance however I am looking for more advice and information from users on how to simulate this in 3D. The variation across the die from the logic positions will affect this significantly and I don’t believe using a uniform power source is correct. Thanks, Max

[EngWei_O_Intel]

Hi Max

In the link below:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html ,

under "Tools, Models and Libraries", there is Flotherm Models for various FPGA devices. We can use 3rd party tools to analyse the model. Let me know if this helps.

Thanks

Eng Wei

[MTayl21]

Hi Eng, I currently do not use Flotherm or Ansys so cannot read these files. Are you able to export them to a solidwokrs compatible format? I have used the Flotherm models but these do not describe technically how the power source should realistically be applied. I believe that they assume a uniform power dissipation across the die area which is very pessimistic. Can you advise how these models are created and against what testing are they verified? Thanks, Max

[EngWei_O_Intel]

Hi Max

Sorry that I am not aware of conversion of Flotherm model to solidwork model.

Can you refer to following doc on Thermal Modelling details?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an787.pdf

Thanks.

Eng Wei

[MTayl21]

Hi Eng Wei, Yes that’s the document I was referring to which shows a thermal gradient on the device, but that methodology only assumes you apply an even power source to the FPGA die, which is hugely unrealistic. I’m hopefully looking for other people who have researched into accurately modelling an FPGA for thermal results, which is more reflective of a typical FPGA logic utilization. Even if that cant reliably be done, possibly some information as to what the accuracy of the Intel method actually is? Thanks, Max

[EngWei_O_Intel]

Hi Max

I have gotten a response from engineering team that Solidworks model might be able to get generated for certain device. May I know if you need it and if yes, which FPGA device are you using?

Thanks.

Eng Wei

[MTayl21]

Hi Eng Wei,

Possibly, it depends how the power should be applied in the model. I've used the available items before and they assume an even power distribution which is inaccurate.

I'm pretty sure my question can't be answered using Intel's standard toolkit, as it needs a much more detailed picture of the FPGA device use. In all the Intel documentation these models give at best a 10% inaccuracy in the model results and I'm looking to narrow that down by a factor of 10.

Thanks,

Max

[EngWei_O_Intel]

Hi Max

Let me know if you have further needs on any specific model that I can help propagate to the engineering team if the solution isn't available now.

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi Max

Do you need any further help such as Solidworks model and etc before we proceed to close the ticket?

Thanks.

Eng Wei

[MTayl21]

Hi Eng Wei,

Are you able to put me in touch with a chip developer who could discuss this with me in more detail?

Thanks,

Max

[EngWei_O_Intel]

Hi Max

The designer might not be able to get connected to the forum platform directly here. We can try to propagate to the engineering team if you have any requirement on specific area.

Thanks.

Eng Wei

[MTayl21]

Hi Eng Wei, Yes that would be very helpful. I cannot see a direct opportunity to discuss through the partner program. Thanks, Max

[EngWei_O_Intel]

Hi Max

Which roadblock specifically you need help including those tools we have mentioned previously? 

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi Max

We do not receive any response from you to the previous feedback that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei