I’m trying to get the Ethernet 1G/10G MAC example design to run on the Arria 10 SoC dev kit. The document here (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-20016.pdf, page 33, Figure 20) indicates that an external clock of 644.53125 MHz for “pll_ref_clk_10g” is among the required clocks. However, I’ve had trouble finding a suitable clock.
First of all, I can only connect the “pll_ref_clk_10g” signal to one of the clock pins in the columns 28/29 (as shown in Quartus’s Pin Planner) that are labeled as “dedicated transceiver”. Among them, I found only 2 pairs of LVDS clock pins that are configurable with the ClockController.exe tool (that comes with the Arria 10 SX SoC Package Installer):
These pins come from U50, which in the schematic is shown to be Si5338B-CUSTOM. Unfortunately, according to the datasheet of the Si5338 device (https://www.silabs.com/documents/public/data-sheets/Si5338.pdf, page 37), an Si5338B can output only a maximum frequency of 350 MHz. I also wrote some test code that uses the clocks to blink an LED. Whenever I used ClockController.exe to set the frequency higher than 350 MHz, the LED would stop blinking.
Then I looked at the clocks from U26, as shown in the Figure 5-3 of the Arria 10 SoC Dev Kit User Guide. I found 2 pairs of clock signals from U26 that are readily connected to the FPGA: PIN_L29/28 and PIN_AR29/28. However, one pair seems to have a frequency of ~400 MHz and the other one seems to have a frequency that is even much lower.
Yes you are correct, Let me check and update on the issues.
Meanwhile can you try this
Hope this helps.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
Thank you for your reply.
The U42 CLK_3Ep & CLK_3En pins connect to the W5 & W6 pins of the FPGA. When I tried connecting the "ref_clk_10g" signal to the W5 & W6 pins, I got the following errors during the Planning stage of the compilation:
* Error (11192): Input port "REF_IQCLK" of "HSSI_PMA_CDR_REFCLK_SELECT_MUX" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for atom "ref_clk_10g~input".
* Error (11192): Input port "REF_IQCLK" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" cannot connect to PLD port "O" of "IO_INPUT_BUFFER" for atom "ref_clk_10g~input".
It seems that the high speed ref clock signal can connect only to pins in the columns 28/29 labeled as "dedicated transceiver" of the FPGA.
Furthermore, when I created test code that uses the U42 pins for blinking an LED, the LED would stop blinking as expected whenever I used the ClockController.exe program to increase the clock speed to over 250 MHz.
Hello Binh and Anand,
I have the same problem… unfortunately…
But, maybe, somebody can to explain me – How to reconfigure U26 (LMK04828) by “TI GUI port” (through FTDI converter FT245RQ) with some “free software”? (or I need, for the first, to write myself app and then write REG’s on U26 and, after all, set “gold” 644.xxx MHz???) (numerous downloaded app’s (for different EVB which contain LMK04828) (and which can work with FTDI converter) from TI won’t work with this “no name” device… unfortunately…)
Moreover Si5338 settings can’t be saved in internal mem like EEPROM or similar…
Sorry for my English…