The development board is "stratix IV GX FPGA development board,530 edition". As the description in the reference manual, I program the CPLD PFL .pof into MAX II CPLD and it can configure the FPGA from flash memory. Before programming, the programmer can setup hardware while after programming, the JTAG errors happen and no hardware detect. After power up again, I can find USB-blaster and auto detect the device. However, the JTAG server error happened again after auto detect. I assume it's because of the .pof file in CPLD while I cannot erase it because of the JTAG server issue.
SW4.1 OFF, SW4.2 OFF, SW4.3 ON, SW4.4 OFF, SW4.5 ON, SW4.6 ON, SW4.7 ON, SW4.8 OFF. SW6.1 OFF, SW6.2 ON, SW6.3 ON, SW6.4 ON. I'm using embedded USB-Blaster. The SW4&SW6 settings have not changed. Before the programming from flash using CPLD, I can program over embedded USB-Blaster. The file programmed into CPLD may result in JTAG issue after auto detect. I'm confused how can I erase CPLD in the condition no hardware setup in programmer. It's quite urgent. Thanks!