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How to make clk and loaden of external PLL for altlvds on cylone 10?

Lambert
New Contributor I
242 Views

Hi everyone,

When I use Arria V to implement high-speed lvds output, I use altlvds ip with external Pll, I need altera_pll_lvds_output to make clk and loaden outputed from external pll as lvds signal for the clk and load of altlvds? But when I use Cyclone 10, which primitive I need like altera_pll_lvds_output?

Best regards,

lambert​

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2 Replies
Lambert
New Contributor I
115 Views

Because now the lvds serdes module has integrated lvds clock tree.​

Rahul_S_Intel1
Employee
115 Views

In Cyclone 10 GX ,

the serdes is using altera lvds ip not alt lvds ip

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf

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