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5275 Discussions

How to read data in FPGA out of external DDR3 SDRAM on an Terasic DE10-Nano

JGros12
Beginner
1,244 Views

Hello everybody,

 

 

I have the Terasic DE10 Nano in a Cyclon V-SoC with 1 GB of external RAM. I can access the working memory via HPS (C code). So I can write values to a specific address space. Now I have to read these addresses in the FPGA. I know I need to add the F2H_SDRAM bridge, but I do not know how to write the VHDL code and the rest of the material.

 

I have already reserved some memory (512 MB for Linux) in u-boot.

 

 

For example, I would like to turn on an LED if the value is 48 in a particular DDR3 address.

 

I just want to read the DDR3 address space. That's all.

 

 

Can someone help me or give me a code? ....

 

 

Many thanks

 

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5 Replies
EBERLAZARE_I_Intel
630 Views

Hi,

 

To enable FPGA2SDRAM Bridge, you can do it from the Preloader or U-boot:

>from U-Boot:

At the U-boot command prompt add:

run bridge_enable_handoff

*This command puts the HPS and SDRAM into a safe state before enabling all bridges after appropriate checks.

 

> Can someone help me or give me a code? (to read the DDR3 address space):

There is actually a sample code from Terasic website on you specific board, on Nios access DDR3, you will need an account when clicking the Download link.

Jump to CD-ROM > DE10-Nano CD-ROM (rev. C Hardware) > Download:

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046&PartNo=4

 

Extract thenyou can find the project file example in > DE10-Nano_v.1.3.5_HWrevC_SystemCD\Demonstrations\SoC_FPGA\Nios_Access_DDR3

 

Feel free to ask if you have further questions.

 

Regards.

JGros12
Beginner
630 Views

Thank you for your answer.

 

I have already seen the Nios_Access_DDR3 example.

My question is: Is there another way to access the addresses without DMA and NIOS? I would like to read the data only with VHDL / VERILOG code.

 

Regards.

EBERLAZARE_I_Intel
630 Views

Hi,

 

There might be other way to access the addresses, but there are none from Intel that have the sample code that represent the address access.

Except the example that I provided which is external which is the Nios Access DDR3 example.

 

You may find some useful examples here:

https://github.com/robertofem/CycloneVSoC-examples

 

Regards.

JGros12
Beginner
630 Views

Hi,

 

thanks for your quick reply.

What do you think about the DDR3_RTL example (TERASIC GHRD). Maybe I can use this as an startpoint for my application.

EBERLAZARE_I_Intel
630 Views

Hi,

 

Yes, I would recommend the the example as it demonstrate the FPGA site to access the DDR3 at HPS.

 

From there you can understand how the f2h bridge interfaces, etc..

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