How to read differential data in double-datarate mode using differential clock for an RF transceiver

[Sivakumar_S]

Hi ,

In my design there is a RF transceiver (with Arria10 SoC), which has differential data which is in double data rate mode. Also the data clock (3.84MHz)and frame clock is of differential mode.

So, how can I read the ADC data  with clocks which is of differential mode. In GPIO IP there is an option for differential to the datain or dataout but not for clocks. Can I connect the differential clock p to the the one clock pin? 

I checked the GPIO IP, but in the User guide they have mentioned " The GPIO Intel® FPGA IP core supports the general purpose I/O (GPIO) features and components. You can use GPIOs in general applications that are not specific to transceivers, memory interfaces, or LVDS. "

I also checked the LVDS IP, but there minimum supported data clock is around 100MHz.

[FvM]

You design the intended logic and connect any IO standard of your choice. Differential IO standards use a single port pin. No need for special IO IP.

[ZiYing_Intel]

Hi,

I think you can try to use the PHY Lite for Parallel Interfaces Intel FPGA IP as it also can support for the double data rate. For further information about this IP, please do refer the UG in link below, https://www.intel.com/content/www/us/en/docs/programmable/683716/23-1/about-the-ip.html

Best regards,

Zi Ying

[ZiYing_Intel]

Hi,

Since long time no hear from you, I am now close the issue. If you have any question after the case closed, please do feel free to submit another issue.

Best regards,

Zi Ying