I am working with the cyclone V device.Currently i am processing the lvds signals.

[JGeor12]

The major problem is, i cannot route the input lvds signal between the input to the LVDS_RX IP and input to the lcd externally connected at the same time.Either as input to the lcd or IP is possible.Is there any way for routing the lvds signal simultaneously to both the inputs.

I have already asked the same question in intel forum,but didn't get any response.Since it is very urgent,kindly give the answer as soon as possible.

[SreekumarR_G_Intel]

I am not getting your question ; You were saying you are not able to connect the output of the LVDS IP to your LCD ?

Would it possible to share the deisgn to check quickly ?

Thank you ,

Regards,

Sree

[JGeor12]

The output of ip is not connected to the lcd. The input of this lcd is lvds signals.So here the problems is , i can't give lvds signals as input to RX ip and LCD at the same time.only one is possible.

[SreekumarR_G_Intel]

i am really not getting your questions , Kindly attach the design and error message ..i will work on it and try to give the soultion if i can.

Thanks

[JGeor12]

I am connecting the LVDS output from a board A1 to the custom board with FPGA 5CEBA2F23C8. This is then transmitted to HDMI interface. I also need to loopback the LVDS data coming to the custom board to an LCD. But while compiling in Quartus some errors are occuring in 'Fitter( (Place and Route)'

The following are the error messages:

Error (170143): Final fitting attempt was unsuccessful

Info (170138): Failed to route the following 6 signal(s)

Info (170139): Signal "lvdse_in[0]~input"

Info (170139): Signal "lvdse_in[4]~input"

Info (170139): Signal "lvdse_in[1]~input"

Info (170139): Signal "lvdse_in[5]~input"

Info (170139): Signal "lvdse_in[2]~input"

Info (170139): Signal "lvdse_in[6]~input"

[SreekumarR_G_Intel]

Can you attach the design ? There is a way you to attach the design privtaely in the fourm if you think design is confidential.

or attcah the smillar design only with IP and interface part and replicate the error.

[JGeor12]

The attached file is the verilog file.I have highlighted the part where routing issues occured in the code.While running it i got the below problems.

Error (170143): Final fitting attempt was unsuccessful

Info (170138): Failed to route the following 6 signal(s)

Info (170139): Signal "lvdse_in[0]~input"

Info (170139): Signal "lvdse_in[4]~input"

Info (170139): Signal "lvdse_in[1]~input"

Info (170139): Signal "lvdse_in[5]~input"

Info (170139): Signal "lvdse_in[2]~input"

Info (170139): Signal "lvdse_in[6]~input"

[SreekumarR_G_Intel]

hey buddy, why not just qar files :)..you have i have to look at your design and instantiated all the IP.

can you please send me the qar files ?

In quartus -> project Arch project -> (Generate .qar )

[JGeor12]

I have attached the QAR file

[SreekumarR_G_Intel]

Thank you for the qar file ; you are getting this error since you are connecting the reference clk input to the LVDS channel and the fifo.

Quartus wont be able to route the same .

Can you use the other fabric clock in FIFO instead of lvdse_clk ?

[JGeor12]

Thank you for the reply.But actually the fifo is not fed by the input lvds clock ,it is fed by the output clock of LVDS_RX ip and it is used for writing .So can you check it and specify on clocks.