I have cyclone 10 lp FPGA with cypress serial flash as the configuration device. In order to burn my firmware to the flash (using jtag and Active Serial mode) I want to use pof file. Is it a problem?

[Vicky1]

Hi,

As in the post Quartus tool edition/version & part number of cypress serial flash are missing so I would like to suggest the following various solution

1.First try with .pof file with “Disable EPCS ID Check” except Quartus tool v12 & v13

http://www.cypress.com/file/195256/download

2.Try with Jtag Indirect file(.jic) with “Disable EPCS ID Check” However, if the Quartus Programmer cannot properly detect the Cypress device, then refer the link below for an alternate method to in-system program the Cypress SPI flash by using Altera’s Nios II tool, which works with all versions of Quartus tool.

http://www.cypress.com/file/202476/download

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[NZami]

Hi, is it possible to work with .pof file when working with Active Serial mode? We used to work with .pof file but we worked with Active Parallel mode and with parallel flash.

Niv.

[Vicky1]

Hi,

Have you tried the various approaches mentioned in previous post?

please provide screenshot if you came across any error.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[NZami]

Hi vicky, I hope you can help me, I have problem to generate the jic file. I generate new NIOS and generate code with eclipse (elf file). From the elf file I generate HEX file for initial the NIOS processor. After synthesis my code I burn the sof file to my board and its work. When I try to generate the jic file I get error the HEX file is not good and that "data in HEX file is overlaps between data blocks at address 8 and address 0" What is problem and how can I fix that? Niv.