In Arria V (5AGXFB7K4F40I5) I have generated DDR3 memory controller (using Quartus IP catalog). Following power (long time) up signal mem_reset_n is stuck at low though cal_success is at '1' and other controller ouptus seem to OK What coud be reason?

[DShaz1]

Thanks Dan​

[NurAida_A_Intel]

Hi DShaz1,

Thank you for joining this Intel Community.

So far, I never experienced this before thus I am not aware with this situation. But, the possible reason I can think of is it been in idle state for too long because no read/write being issue.

You may want to try generate the example design and run the simulation first and see if there is anything missing in your design.

Hope this helps.

Thanks

Aida