FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5286 Discussions

In Arria V (5AGXFB7K4F40I5) I have generated DDR3 memory controller (using Quartus IP catalog). Following power (long time) up signal mem_reset_n is stuck at low though cal_success is at '1' and other controller ouptus seem to OK What coud be reason?

DShaz1
Beginner
262 Views

Thanks Dan​

0 Kudos
1 Reply
NurAida_A_Intel
Employee
106 Views

Hi DShaz1,

 

Thank you for joining this Intel Community.

 

So far, I never experienced this before thus I am not aware with this situation. But, the possible reason I can think of is it been in idle state for too long because no read/write being issue.

 

You may want to try generate the example design and run the simulation first and see if there is anything missing in your design.

 

Hope this helps.

 

Thanks

 

Aida

 

Reply