Device: 1SM21BHU2F53E2VGS1 (Stratix 10 MX)
Quartus version: 19.2 (19.4 is possible to use)
Connection to host PC from FPGA: JTAG through FPGA Blaster II (USB cable)
Hi, we want to preload HBM memory with some dataset so that we can process that data on FPGA. Is there any way to initialized HBM memory with hex file or binary file? Like .hex file or .mif file it used to be there for this purpose?
Short answer is NO due to HBM IP need to perform calibration for every power up cycle.
Even if we have a way to pre-load the data to memory, it will be overwritten by pre-define training data used in calibration process.
Thanks for the answer and help. But then, how do we initialize HBM? There must be some way of doing it.
I am currently looking into the design example AN881, which has DMA IP, PCIe Hard IP and HBM interface/controller IP.
Isn't it there for the communication between host PC's CPU and HBM through PCIe connection?
By using those IPs, we can give a DMA module some kind of commands that can initialize the HBM memory with dataset we want on the host side.
This will happen after the configuration and calibration finished. Since writing into the HBM thorugh PCIe using DMA module will happen in the USER mode, it won't be affected by the calibration process and the FPGA will retain what we write into the HBM. Isn't it?
Now i understand the difference between your definition of HBM2 initialization vs mine.
My understanding of HBM2 initialization is during FPGA power up, HBM2 IP will initialize HBM2 chipset and then perform calibration. Once calibration completed and successful, user can then perform write/read operation to HBM2
Your understanding of HBM2 initialization in my opinion will be the user mode HBM2 write/read operation.
I visualize what you are trying to perform is as below :
Unfortunately, Intel FPGA doesn't provide customized service on PCIe driver design.
Perhaps you want to consult on other active PCIe forum to get advise on how to do it.
It's been a while since we last communicated. I hope I explained our difficulty on providing customized design service.
Hopefully you manage to find help from other PCIe forum.
For now, I am setting this case to closure.