Hi,I need to use LVDS on the NE0-Nano development kit, and I have a questions with respect to how to go about it. From what I understand, I have two options:
Just a short update.I have managed to get it to work by using differential output buffers. It works fine, but it can only go as fast as the PLL, which for Cyclone IV E speed grade 6 is 472.5MHz. Next step is to get this going with the ALTLVDS megafunction.
Cyclone LVDS Megafunctions is just a software SERDES, using DDR registers. You can write equivalent code in your design.You don't tell the objectives of your project, by the way.
I ma trying to sue FPGA to drive a TFT screen with an FPGA, which results in 7:1 serialisation ratio. My LVDS bit clock is as high as the PLL 472.5MHz, which is not enough for the 60Hz refresh rate.I was hoping megafunction would allow me to get over that obstacle, but I cannot sense the internal clock that achieves the desired data rate of 583Mbps.
I have managed to write my own SER VHDL code. However, the limiting factor is the PLL frequency. FvM, how can I use the DDR register to doouble the frequency? I tried triggering on either clock edge but Quartus kept complaining and I couldn't compile my design. I would be very grateful if you could point me in the right direction.
Here's a LVDS receiver example using altddio_in to implement DDR input registers:
chan: FOR I IN 0 TO N_AD_CHAN - 1 GENERATE lvds_rcv : altddio_in GENERIC MAP ( intended_device_family => "Cyclone III", invert_input_clocks => "ON", lpm_type => "altddio_in", power_up_high => "OFF", width => 1 ) PORT MAP ( datain => AD9222_D(I TO I), inclock => fastclock, dataout_h => dataout_h(I DOWNTO I), dataout_l => dataout_l(I DOWNTO I) ); PROCESS (fastclock) BEGIN IF rising_edge(fastclock) THEN lvds_sr(I) <= lvds_sr(I)(9 downto 0) & dataout_l(I) & dataout_h(I); END IF; END PROCESS; PROCESS (slowclock) BEGIN IF reset = '1' THEN lvds_rx(I) <= (others => '0'); ELSIF rising_edge(slowclock) THEN lvds_rx(I) <= lvds_sr(I); END IF; END PROCESS; END GENERATE;
many thanks for the example, FvM.I got it working, however the development kit cannot handle the speed and I get a fair amount of interference, which was expected. Anyway, thanks again.
I agree, this was more of a hack to be fair. I'm in the process of developing an expansion board for the Nano which will feature hardware LVDS serialisers and sensible connector for the output so I don't have to hack the original panel cable to pieces.I also have another dev kit (SoCKit) which features one of those HSMC connectors, I will take a look and check whether any of those differential output pairs are on 2.5V supply.