LVDS and DE0-Nano

Altera_Forum · ‎01-07-2012

Hi,

I need to use LVDS on the NE0-Nano development kit, and I have a questions with respect to how to go about it.

From what I understand, I have two options:

LVDS megafunction
Parallel out into a LVDS transmitter chip

The problem I am having, is that I would like to use the megafunction but without any input. I would like to configure it so it generates dummy data. This way I can perform some simulations and measurements at the early stage of my project. Once that is working I can add the input and play with some real data. Also, is there another way of using LVDS but not the megafunction?

Any suggestions?

Altera_Forum · ‎02-07-2012

Just a short update.

I have managed to get it to work by using differential output buffers. It works fine, but it can only go as fast as the PLL, which for Cyclone IV E speed grade 6 is 472.5MHz.

Next step is to get this going with the ALTLVDS megafunction.

Altera_Forum · ‎02-07-2012

Cyclone LVDS Megafunctions is just a software SERDES, using DDR registers. You can write equivalent code in your design.

You don't tell the objectives of your project, by the way.

Altera_Forum · ‎02-07-2012

I ma trying to sue FPGA to drive a TFT screen with an FPGA, which results in 7:1 serialisation ratio. My LVDS bit clock is as high as the PLL 472.5MHz, which is not enough for the 60Hz refresh rate.

I was hoping megafunction would allow me to get over that obstacle, but I cannot sense the internal clock that achieves the desired data rate of 583Mbps.

Altera_Forum · ‎05-31-2012

I have managed to write my own SER VHDL code. However, the limiting factor is the PLL frequency. FvM, how can I use the DDR register to doouble the frequency? I tried triggering on either clock edge but Quartus kept complaining and I couldn't compile my design. I would be very grateful if you could point me in the right direction.

Altera_Forum · ‎05-31-2012

Here's a LVDS receiver example using altddio_in to implement DDR input registers:

chan:
FOR I IN 0 TO N_AD_CHAN - 1 GENERATE
	lvds_rcv : altddio_in
	GENERIC MAP (
		intended_device_family => "Cyclone III",
		invert_input_clocks => "ON",
		lpm_type => "altddio_in",
		power_up_high => "OFF",
		width => 1
	)
	PORT MAP (
		datain => AD9222_D(I TO I),
		inclock => fastclock,
		dataout_h => dataout_h(I DOWNTO I),
		dataout_l => dataout_l(I DOWNTO I)
	);
	PROCESS (fastclock)
	BEGIN
      IF rising_edge(fastclock) THEN
         lvds_sr(I) <= lvds_sr(I)(9 downto 0) & dataout_l(I) & dataout_h(I);
		END IF;
	END PROCESS;
	PROCESS (slowclock)
	BEGIN
	   IF reset = '1' THEN
	      lvds_rx(I) <= (others => '0');
      ELSIF rising_edge(slowclock) THEN
         lvds_rx(I) <= lvds_sr(I);
		END IF;
	END PROCESS;
END GENERATE;

Altera_Forum · ‎09-03-2012

many thanks for the example, FvM.

I got it working, however the development kit cannot handle the speed and I get a fair amount of interference, which was expected. Anyway, thanks again.

Altera_Forum · ‎06-01-2015

LVDS is 2.5v but DE0-Nano VCCIO is 3.3v, is fine?

Altera_Forum · ‎06-02-2015

In theory it shouldn't work but it worked fine with the TFT panel I was using. I think those input stages on some TFT panels are quite forgiving.

Altera_Forum · ‎06-02-2015

I think problem is not receiver but output buffer of fpga that can not work safely with 3.3v when configured for 2.5v

Altera_Forum · ‎06-03-2015

There are in fact no differential I/O standard supported for 3.3V VCCIO. "can not work safely" is a different thing.

Altera_Forum · ‎06-03-2015

I agree, this was more of a hack to be fair. I'm in the process of developing an expansion board for the Nano which will feature hardware LVDS serialisers and sensible connector for the output so I don't have to hack the original panel cable to pieces.

I also have another dev kit (SoCKit) which features one of those HSMC connectors, I will take a look and check whether any of those differential output pairs are on 2.5V supply.