Logic levels on Pins from the Factory

[aWild8]

What logic levels do the pins on the 10M50DCF484I7C float to from the factory?

aka, when I plug this chip into my PCB for the first time before programming it are the pins floating, pulled low, pulled high. Is it a strong pull or a weak pull?

I have had issues in the past with the floating logic levels destroying parts of my circuit because the FPGA is not there to pull signals high.

[SreekumarR_G_Intel]

Are you asking state of the Max 10 FPGA IO at reset state ? if yes , answer to your questions is Tri-State.

Thank you,

Regards,

Sree

[aWild8]

Not the logic levels at the reset state. but the logic levels on the pins right when I take the chip out of the box and power it on.

If the chip is in a reset state straight out of the box then this does answer the question.

[SreekumarR_G_Intel]

Flow chart page no : 28/67 below link information about the Configuration Sequence for Intel MAX 10 Devices and each stage IO lines state too.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

Thank you ,

Regards,

Sree