Pull up or down of DCLK and DATA[0] pin of FPGA

[weid]

Hi,

I wonder how to handle the DCLK and DATA[0] pin of FPGA.

a. The datasheet says that these pins must be pulled high or low after configuration for JTAG mode(can't folat).

b. However, the datasheet also says that these pins have an internal pullup (25K typical) that is always active at AS mode. So, this seems to be contradictory information.

Looks now I use both the JTAG and AS mode with same JTAG port, I use JTAG mode debug the Nios source code also use JTAG port to download firmware to EPCS flash with the NIOS "EPCS_controller" use AS mode, so, whether I need add poll down or up resistor for these pin?

[JohnT_Intel]

Hi,

May I know which device are you refering to?

Answer to your question.

a. This is only apply if you are using JTAG configuration without any other configuration mode. The datasheet is mentioning this pin to have high or low so that the pin is not left floating.

b. Since you are using AS and JTAG mode then you need to follow the AS connection guideline. The reason is that the DCLK and DATA0 is used by AS interface. No pull up or down resistor is needed for this pin. You may refer to the connection guideline in FPGA Configuration Chapter document.

[weid]

​Hi, the device is Cyclone 4 EP4CE40.

I guess I got the answer from your reply, but sill have a little bit confuse.

When module power up, in my project, FPGA will get firmware from EPCS flash use AS mode.

"All AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have weak internal pullup resistors that are always active. After configuration, these pins are set as input tristate and are driven high by the weak internal pull-up resistors."

As datasheet said, these pin have weak internal pullup resistor that are always active.

But, I also need use JATG mode to download the .sof file to FPGA to debug, for JTAG configuration chapter, in datasheet, Note of Figure 8-23 also said: "In addition, pull DCLK and DATA[0] to either high or low, whichever is convenient on your board.", look it ask that we should pull these 2 pin on outside of the PFGA with resistor.

So, whether the weak internal pullup resistor is always active only for AS mode? or, is always active for all the mode? if it is , why datasheet ask us to pull them again outside the FPGA.

Please helps to take a look this, very thank.

[JohnT_Intel]

Hi,

The datasheet mention on connecting it to high or low when you are using JTAG mode only. So if you are using both JTAG and AS configuration mode then you do not need to weak-pull up it.

The internal weak-pull up on the DCLK pin will depends on your Quartus setting after entering usermode. Before entering usermode the DCLK pin will have weakpull-up active. No weakpull up on DATA0 pin.